| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2015 Intel Corp. |
| * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <device/device.h> |
| #include <intelblocks/systemagent.h> |
| #include <soc/iomap.h> |
| #include <soc/systemagent.h> |
| |
| /* |
| * SoC implementation |
| * |
| * Add all known fixed memory ranges for Host Controller/Mmeory |
| * controller. |
| */ |
| void soc_add_fixed_mmio_resources(struct device *dev, int *index) |
| { |
| static const struct sa_mmio_descriptor soc_fixed_resources[] = { |
| { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, |
| "PCIEXBAR" }, |
| { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, |
| }; |
| |
| sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, |
| ARRAY_SIZE(soc_fixed_resources)); |
| } |