Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #ifndef HASWELL_RAMINIT_NATIVE_H |
| 4 | #define HASWELL_RAMINIT_NATIVE_H |
| 5 | |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 6 | #include <device/dram/ddr3.h> |
| 7 | #include <northbridge/intel/haswell/haswell.h> |
| 8 | |
| 9 | #define SPD_LEN 256 |
| 10 | |
| 11 | /* 8 data lanes + 1 ECC lane */ |
| 12 | #define NUM_LANES 9 |
| 13 | #define NUM_LANES_NO_ECC 8 |
| 14 | |
Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 15 | enum raminit_boot_mode { |
| 16 | BOOTMODE_COLD, |
| 17 | BOOTMODE_WARM, |
| 18 | BOOTMODE_S3, |
| 19 | BOOTMODE_FAST, |
| 20 | }; |
| 21 | |
| 22 | enum raminit_status { |
| 23 | RAMINIT_STATUS_SUCCESS = 0, |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 24 | RAMINIT_STATUS_NO_MEMORY_INSTALLED, |
| 25 | RAMINIT_STATUS_UNSUPPORTED_MEMORY, |
Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 26 | RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/ |
| 27 | }; |
| 28 | |
| 29 | enum generic_stepping { |
| 30 | STEPPING_A0 = 1, |
| 31 | STEPPING_B0 = 2, |
| 32 | STEPPING_C0 = 3, |
| 33 | }; |
| 34 | |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 35 | struct raminit_dimm_info { |
Elyes Haouas | 78ba7a7 | 2024-05-06 05:11:28 +0200 | [diff] [blame] | 36 | spd_ddr3_raw_data raw_spd; |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 37 | struct dimm_attr_ddr3_st data; |
| 38 | uint8_t spd_addr; |
| 39 | bool valid; |
| 40 | }; |
| 41 | |
Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 42 | struct sysinfo { |
| 43 | enum raminit_boot_mode bootmode; |
| 44 | enum generic_stepping stepping; |
| 45 | uint32_t cpu; /* CPUID value */ |
| 46 | |
| 47 | bool dq_pins_interleaved; |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 48 | |
| 49 | /** TODO: ECC support untested **/ |
| 50 | bool is_ecc; |
| 51 | |
| 52 | /** |
| 53 | * FIXME: LPDDR support is incomplete. The largest chunks are missing, |
| 54 | * but some LPDDR-specific variations in algorithms have been handled. |
| 55 | * LPDDR-specific functions have stubs which will halt upon execution. |
| 56 | */ |
| 57 | bool lpddr; |
| 58 | |
| 59 | struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS]; |
| 60 | union dimm_flags_ddr3_st flags; |
| 61 | uint16_t cas_supported; |
| 62 | |
| 63 | /* Except for tCK, everything is eventually stored in DCLKs */ |
| 64 | uint32_t tCK; |
| 65 | uint32_t tAA; /* Also known as tCL */ |
| 66 | uint32_t tWR; |
| 67 | uint32_t tRCD; |
| 68 | uint32_t tRRD; |
| 69 | uint32_t tRP; |
| 70 | uint32_t tRAS; |
| 71 | uint32_t tRC; |
| 72 | uint32_t tRFC; |
| 73 | uint32_t tWTR; |
| 74 | uint32_t tRTP; |
| 75 | uint32_t tFAW; |
| 76 | uint32_t tCWL; |
| 77 | uint32_t tCMD; |
| 78 | |
| 79 | uint8_t lanes; /* 8 or 9 */ |
| 80 | uint8_t chanmap; |
| 81 | uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */ |
| 82 | uint8_t rankmap[NUM_CHANNELS]; |
| 83 | uint8_t rank_mirrored[NUM_CHANNELS]; |
| 84 | uint32_t channel_size_mb[NUM_CHANNELS]; |
Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | void raminit_main(enum raminit_boot_mode bootmode); |
| 88 | |
Angel Pons | 1b25422 | 2022-05-07 13:48:53 +0200 | [diff] [blame] | 89 | enum raminit_status collect_spd_info(struct sysinfo *ctrl); |
| 90 | |
Angel Pons | 1c9a8d8 | 2022-05-07 00:26:10 +0200 | [diff] [blame] | 91 | #endif |