Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 1 | if BOARD_SUPERMICRO_H8SCM_FAM10 |
| 2 | |
| 3 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 4 | def_bool y |
| 5 | select ARCH_X86 |
Siyuan Wang | 1fb49df | 2012-09-07 18:35:17 +0800 | [diff] [blame^] | 6 | select CPU_AMD_SOCKET_C32_NON_AGESA |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 7 | select DIMM_DDR3 |
| 8 | select DIMM_REGISTERED |
| 9 | select NORTHBRIDGE_AMD_AMDFAM10 |
| 10 | select SOUTHBRIDGE_AMD_SR5650 |
Kyösti Mälkki | 399fcdd | 2012-02-23 18:42:55 +0200 | [diff] [blame] | 11 | select SOUTHBRIDGE_AMD_SB700 |
| 12 | select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 13 | select SUPERIO_WINBOND_W83627HF |
Alexandru Gagniuc | 1a2b318 | 2011-08-03 09:14:59 -0500 | [diff] [blame] | 14 | select SUPERIO_NUVOTON_WPCM450 |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 15 | select HAVE_BUS_CONFIG |
| 16 | select HAVE_OPTION_TABLE |
| 17 | select GENERATE_PIRQ_TABLE |
| 18 | select GENERATE_MP_TABLE |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 19 | select SB_HT_CHAIN_UNITID_OFFSET_ONLY |
| 20 | select LIFT_BSP_APIC_ID |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 21 | select SERIAL_CPU_INIT |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 22 | select AMDMCT |
| 23 | select GENERATE_ACPI_TABLES |
| 24 | select BOARD_ROMSIZE_KB_2048 |
| 25 | select RAMINIT_SYSINFO |
| 26 | select ENABLE_APIC_EXT_ID |
Zheng Bao | 910f4ca | 2011-03-28 04:38:14 +0000 | [diff] [blame] | 27 | |
| 28 | config MAINBOARD_DIR |
| 29 | string |
| 30 | default supermicro/h8scm_fam10 |
| 31 | |
| 32 | config APIC_ID_OFFSET |
| 33 | hex |
| 34 | default 0x0 |
| 35 | |
| 36 | config MAINBOARD_PART_NUMBER |
| 37 | string |
| 38 | default "H8SCM (Fam10)" |
| 39 | |
| 40 | config MAX_CPUS |
| 41 | int |
| 42 | default 16 |
| 43 | |
| 44 | config MAX_PHYSICAL_CPUS |
| 45 | int |
| 46 | default 1 |
| 47 | |
| 48 | config MEM_TRAIN_SEQ |
| 49 | int |
| 50 | default 2 |
| 51 | |
| 52 | config SB_HT_CHAIN_ON_BUS0 |
| 53 | int |
| 54 | default 1 |
| 55 | |
| 56 | config HT_CHAIN_END_UNITID_BASE |
| 57 | hex |
| 58 | default 0x1 |
| 59 | |
| 60 | config HT_CHAIN_UNITID_BASE |
| 61 | hex |
| 62 | default 0x0 |
| 63 | |
| 64 | config IRQ_SLOT_COUNT |
| 65 | int |
| 66 | default 11 |
| 67 | |
| 68 | config AMD_UCODE_PATCH_FILE |
| 69 | string |
| 70 | default "mc_patch_010000c4.h" |
| 71 | |
| 72 | config RAMTOP |
| 73 | hex |
| 74 | default 0x2000000 |
| 75 | |
| 76 | config HEAP_SIZE |
| 77 | hex |
| 78 | default 0xc0000 |
| 79 | |
| 80 | config ACPI_SSDTX_NUM |
| 81 | int |
| 82 | default 0 |
| 83 | |
| 84 | config RAMBASE |
| 85 | hex |
| 86 | default 0x200000 |
| 87 | |
| 88 | endif # BOARD_AMD_H8SCM_FAM10 |