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Zheng Bao910f4ca2011-03-28 04:38:14 +00001if BOARD_SUPERMICRO_H8SCM_FAM10
2
3config BOARD_SPECIFIC_OPTIONS # dummy
4 def_bool y
5 select ARCH_X86
6 select CPU_AMD_SOCKET_C32
7 select DIMM_DDR3
8 select DIMM_REGISTERED
9 select NORTHBRIDGE_AMD_AMDFAM10
10 select SOUTHBRIDGE_AMD_SR5650
11 select SOUTHBRIDGE_AMD_SP5100
12 select SUPERIO_WINBOND_W83627HF
13 select HAVE_BUS_CONFIG
14 select HAVE_OPTION_TABLE
15 select GENERATE_PIRQ_TABLE
16 select GENERATE_MP_TABLE
17 select HAVE_MAINBOARD_RESOURCES
18 select HAVE_HARD_RESET
19 select SB_HT_CHAIN_UNITID_OFFSET_ONLY
20 select LIFT_BSP_APIC_ID
21 select SERIAL_CPU_INIT
22 select AMDMCT
23 select GENERATE_ACPI_TABLES
24 select BOARD_ROMSIZE_KB_2048
25 select RAMINIT_SYSINFO
26 select ENABLE_APIC_EXT_ID
27 select GFXUMA
28
29config MAINBOARD_DIR
30 string
31 default supermicro/h8scm_fam10
32
33config APIC_ID_OFFSET
34 hex
35 default 0x0
36
37config MAINBOARD_PART_NUMBER
38 string
39 default "H8SCM (Fam10)"
40
41config MAX_CPUS
42 int
43 default 16
44
45config MAX_PHYSICAL_CPUS
46 int
47 default 1
48
49config MEM_TRAIN_SEQ
50 int
51 default 2
52
53config SB_HT_CHAIN_ON_BUS0
54 int
55 default 1
56
57config HT_CHAIN_END_UNITID_BASE
58 hex
59 default 0x1
60
61config HT_CHAIN_UNITID_BASE
62 hex
63 default 0x0
64
65config IRQ_SLOT_COUNT
66 int
67 default 11
68
69config AMD_UCODE_PATCH_FILE
70 string
71 default "mc_patch_010000c4.h"
72
73config RAMTOP
74 hex
75 default 0x2000000
76
77config HEAP_SIZE
78 hex
79 default 0xc0000
80
81config ACPI_SSDTX_NUM
82 int
83 default 0
84
85config RAMBASE
86 hex
87 default 0x200000
88
89endif # BOARD_AMD_H8SCM_FAM10