Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 6d9a0eab702213514cc7fba8d0a71c39b2a14585 / . / src / soc / amd / cezanne / root_complex.c
blob: ba846810c805859a80e7723cadf067c9a2fab293 [file] [log] [blame]
Raul E Rangelcf6dc7d2021-02-05 16:00:41 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Raul E Rangel0b123dd2021-02-12 15:13:57 -0700[diff] [blame]3#include <amdblocks/acpi.h>
Raul E Rangelcf6dc7d2021-02-05 16:00:41 -0700[diff] [blame]4#include <amdblocks/memmap.h>
5#include <cbmem.h>
6#include <console/console.h>
7#include <cpu/amd/msr.h>
8#include <device/device.h>
9#include <device/pci.h>
10#include <device/pci_ids.h>
11#include <fsp/util.h>
12#include <stdint.h>
13
14/*
15 *
16 * +--------------------------------+
17 * | |
18 * | |
19 * | |
20 * | |
21 * | |
22 * | |
23 * | |
24 * reserved_dram_end +--------------------------------+
25 * | |
26 * | verstage (if reqd) |
27 * | (VERSTAGE_SIZE) |
28 * +--------------------------------+ VERSTAGE_ADDR
29 * | |
30 * | FSP-M |
31 * | (FSP_M_SIZE) |
32 * +--------------------------------+ FSP_M_ADDR
33 * | romstage |
34 * | (ROMSTAGE_SIZE) |
35 * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
36 * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
37 * | bootblock |
38 * | (C_ENV_BOOTBLOCK_SIZE) |
39 * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
40 * | Unused hole |
41 * | (86KiB) |
42 * +--------------------------------+
43 * | FMAP cache (FMAP_SIZE) |
44 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
45 * | Early Timestamp region (512B) |
46 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
47 * | Preram CBMEM console |
48 * | (PRERAM_CBMEM_CONSOLE_SIZE) |
49 * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
50 * | PSP shared (vboot workbuf) |
51 * | (PSP_SHAREDMEM_SIZE) |
52 * +--------------------------------+ PSP_SHAREDMEM_BASE
53 * | APOB (64KiB) |
54 * +--------------------------------+ PSP_APOB_DRAM_ADDRESS
55 * | Early BSP stack |
56 * | (EARLYRAM_BSP_STACK_SIZE) |
57 * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
58 * | DRAM |
59 * +--------------------------------+ 0x100000
60 * | Option ROM |
61 * +--------------------------------+ 0xc0000
62 * | Legacy VGA |
63 * +--------------------------------+ 0xa0000
64 * | DRAM |
65 * +--------------------------------+ 0x0
66 */
67static void read_resources(struct device *dev)
68{
69 uint32_t mem_usable = (uintptr_t)cbmem_top();
70 unsigned int idx = 0;
71 const struct hob_header *hob = fsp_get_hob_list();
72 const struct hob_resource *res;
73
74 uintptr_t early_reserved_dram_start, early_reserved_dram_end;
75 const struct memmap_early_dram *e = memmap_get_early_dram_usage();
76
77 early_reserved_dram_start = e->base;
78 early_reserved_dram_end = e->base + e->size;
79
80 /* 0x0 - 0x9ffff */
81 ram_resource(dev, idx++, 0, 0xa0000 / KiB);
82
83 /* 0xa0000 - 0xbffff: legacy VGA */
84 mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
85
86 /* 0xc0000 - 0xfffff: Option ROM */
87 reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
88
89 /* 1MiB - bottom of DRAM reserved for early coreboot usage */
90 ram_resource(dev, idx++, (1 * MiB) / KiB,
91 (early_reserved_dram_start - (1 * MiB)) / KiB);
92
93 /* DRAM reserved for early coreboot usage */
94 reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
95 (early_reserved_dram_end - early_reserved_dram_start) / KiB);
96
97 /*
98 * top of DRAM consumed early - low top usable RAM
99 * cbmem_top() accounts for low UMA and TSEG if they are used.
100 */
101 ram_resource(dev, idx++, early_reserved_dram_end / KiB,
102 (mem_usable - early_reserved_dram_end) / KiB);
103
104 mmconf_resource(dev, MMIO_CONF_BASE);
105
106 if (!hob) {
107 printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n",
108 __func__);
109 return;
110 }
111
112 for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) {
113
114 if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
115 continue;
116
117 res = fsp_hob_header_to_resource(hob);
118
119 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
120 continue; /* 0 through low usable was set above */
121 if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
122 continue; /* Done separately */
123
124 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
125 ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
126 else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
127 reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
128 else
129 printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
130 res->type);
131 }
132}
133
Raul E Rangel0b123dd2021-02-12 15:13:57 -0700[diff] [blame]134static void root_complex_fill_ssdt(const struct device *device)
135{
136 acpi_fill_root_complex_tom(device);
137}
138
Felix Heldb28401302021-02-17 00:05:34 +0100[diff] [blame]139static const char *gnb_acpi_name(const struct device *dev)
140{
141 return "GNB";
142}
143
Raul E Rangelcf6dc7d2021-02-05 16:00:41 -0700[diff] [blame]144static struct device_operations root_complex_operations = {
145 .read_resources = read_resources,
146 .set_resources = noop_set_resources,
147 .enable_resources = pci_dev_enable_resources,
Felix Heldb28401302021-02-17 00:05:34 +0100[diff] [blame]148 .acpi_name = gnb_acpi_name,
Raul E Rangel0b123dd2021-02-12 15:13:57 -0700[diff] [blame]149 .acpi_fill_ssdt = root_complex_fill_ssdt,
Raul E Rangelcf6dc7d2021-02-05 16:00:41 -0700[diff] [blame]150};
151
152static const struct pci_driver family17_root_complex __pci_driver = {
153 .ops = &root_complex_operations,
154 .vendor = PCI_VENDOR_ID_AMD,
155 .device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB,
156};