Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/apob_cache.h> |
| 4 | #include <amdblocks/memmap.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 5 | #include <assert.h> |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 6 | #include <console/uart.h> |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 7 | #include <device/device.h> |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 8 | #include <fsp/api.h> |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 9 | #include <soc/platform_descriptors.h> |
| 10 | #include <string.h> |
| 11 | #include <types.h> |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 12 | #include "chip.h" |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 13 | |
| 14 | static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, |
| 15 | const fsp_dxio_descriptor *descs, size_t num) |
| 16 | { |
| 17 | size_t i; |
| 18 | |
| 19 | ASSERT_MSG(num <= FSPM_UPD_DXIO_DESCRIPTOR_COUNT, |
| 20 | "Too many DXIO descriptors provided."); |
| 21 | |
| 22 | for (i = 0; i < num; i++) { |
| 23 | memcpy(mcfg->dxio_descriptor[i], &descs[i], sizeof(mcfg->dxio_descriptor[0])); |
| 24 | } |
| 25 | } |
| 26 | |
| 27 | static void fill_ddi_descriptors(FSP_M_CONFIG *mcfg, |
| 28 | const fsp_ddi_descriptor *descs, size_t num) |
| 29 | { |
| 30 | size_t i; |
| 31 | |
| 32 | ASSERT_MSG(num <= FSPM_UPD_DDI_DESCRIPTOR_COUNT, |
| 33 | "Too many DDI descriptors provided."); |
| 34 | |
| 35 | for (i = 0; i < num; i++) { |
| 36 | memcpy(&mcfg->ddi_descriptor[i], &descs[i], sizeof(mcfg->ddi_descriptor[0])); |
| 37 | } |
| 38 | } |
| 39 | |
| 40 | static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) |
| 41 | { |
| 42 | const fsp_dxio_descriptor *fsp_dxio; |
| 43 | const fsp_ddi_descriptor *fsp_ddi; |
| 44 | size_t num_dxio; |
| 45 | size_t num_ddi; |
| 46 | |
| 47 | mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, |
| 48 | &fsp_ddi, &num_ddi); |
| 49 | fill_dxio_descriptors(mcfg, fsp_dxio, num_dxio); |
| 50 | fill_ddi_descriptors(mcfg, fsp_ddi, num_ddi); |
| 51 | } |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 52 | |
| 53 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 54 | { |
| 55 | FSP_M_CONFIG *mcfg = &mupd->FspmConfig; |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 56 | const struct soc_amd_cezanne_config *config = config_of_soc(); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 57 | |
| 58 | mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); |
| 59 | |
| 60 | mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; |
| 61 | mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; |
| 62 | mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; |
| 63 | mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); |
| 64 | mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 65 | mcfg->serial_port_baudrate = get_uart_baudrate(); |
| 66 | mcfg->serial_port_refclk = uart_platform_refclk(); |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 67 | |
Felix Held | d0b5164 | 2021-04-08 22:25:19 +0200 | [diff] [blame] | 68 | /* 0 is default */ |
| 69 | mcfg->ccx_down_core_mode = config->downcore_mode; |
| 70 | mcfg->ccx_disable_smt = config->disable_smt; |
| 71 | |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 72 | /* when stt_control isn't 1, FSP will ignore the other stt values */ |
| 73 | mcfg->stt_control = config->stt_control; |
| 74 | mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; |
| 75 | mcfg->stt_min_limit = config->stt_min_limit; |
| 76 | mcfg->stt_m1 = config->stt_m1; |
| 77 | mcfg->stt_m2 = config->stt_m2; |
| 78 | mcfg->stt_m3 = config->stt_m3; |
| 79 | mcfg->stt_m4 = config->stt_m4; |
| 80 | mcfg->stt_m5 = config->stt_m5; |
| 81 | mcfg->stt_m6 = config->stt_m6; |
| 82 | mcfg->stt_c_apu = config->stt_c_apu; |
| 83 | mcfg->stt_c_gpu = config->stt_c_gpu; |
| 84 | mcfg->stt_c_hs2 = config->stt_c_hs2; |
| 85 | mcfg->stt_alpha_apu = config->stt_alpha_apu; |
| 86 | mcfg->stt_alpha_gpu = config->stt_alpha_gpu; |
| 87 | mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; |
| 88 | mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; |
| 89 | mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; |
| 90 | mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; |
| 91 | mcfg->stt_error_coeff = config->stt_error_coeff; |
| 92 | mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; |
| 93 | |
| 94 | /* all following fields being 0 is a valid config */ |
| 95 | mcfg->stapm_boost = config->stapm_boost; |
Martin Roth | 9c17665 | 2021-04-23 12:24:35 -0600 | [diff] [blame] | 96 | mcfg->stapm_time_constant = config->stapm_time_constant_s; |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 97 | mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; |
Martin Roth | 9c17665 | 2021-04-23 12:24:35 -0600 | [diff] [blame] | 98 | mcfg->sustained_power_limit = config->sustained_power_limit_mW; |
| 99 | mcfg->fast_ppt_limit = config->fast_ppt_limit_mW; |
| 100 | mcfg->slow_ppt_limit = config->slow_ppt_limit_mW; |
Martin Roth | 029d997 | 2021-04-23 12:22:59 -0600 | [diff] [blame] | 101 | mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s; |
| 102 | mcfg->thermctl_limit = config->thermctl_limit_degreeC; |
Felix Held | d3be9ba | 2021-04-19 21:40:35 +0200 | [diff] [blame] | 103 | |
| 104 | /* 0 is default */ |
| 105 | mcfg->smartshift_enable = config->smartshift_enable; |
| 106 | |
| 107 | /* 0 is default */ |
| 108 | mcfg->system_configuration = config->system_configuration; |
| 109 | |
| 110 | /* when cppc_ctrl is 0 the other values won't be used */ |
| 111 | mcfg->cppc_ctrl = config->cppc_ctrl; |
| 112 | mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; |
| 113 | mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range; |
| 114 | mcfg->cppc_epp_max_range = config->cppc_epp_max_range; |
| 115 | mcfg->cppc_epp_min_range = config->cppc_epp_min_range; |
| 116 | mcfg->cppc_preferred_cores = config->cppc_preferred_cores; |
| 117 | |
Karthikeyan Ramasubramanian | 5ad85d9 | 2021-04-22 16:59:08 -0600 | [diff] [blame] | 118 | /* S0i3 enable */ |
| 119 | mcfg->s0i3_enable = config->s0ix_enable; |
| 120 | |
Chris Wang | 0679392 | 2021-04-29 00:11:01 +0800 | [diff] [blame] | 121 | /* voltage regulator telemetry settings */ |
| 122 | mcfg->telemetry_vddcrvddfull_scale_current = |
| 123 | config->telemetry_vddcrvddfull_scale_current_mA; |
| 124 | mcfg->telemetry_vddcrvddoffset = |
| 125 | config->telemetry_vddcrvddoffset; |
| 126 | mcfg->telemetry_vddcrsocfull_scale_current = |
| 127 | config->telemetry_vddcrsocfull_scale_current_mA; |
| 128 | mcfg->telemetry_vddcrsocOffset = |
| 129 | config->telemetry_vddcrsocoffset; |
| 130 | |
Matt Papageorge | ea0f225 | 2021-03-30 11:41:22 -0500 | [diff] [blame] | 131 | fsp_fill_pcie_ddi_descriptors(mcfg); |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 132 | } |