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review.coreboot.org / coreboot / 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 / . / src / cpu / intel / car / non-evict / exit_car.S
blob: 9e37b4644c299e70e362a31ef580279be5fba02f [file] [log] [blame]
Angel Ponsf23ae0b2020-04-02 23:48:12 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]2
Martin Rothc87ab012022-11-20 19:32:51 -0700[diff] [blame]3#include <cpu/intel/post_codes.h>
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]4#include <cpu/x86/mtrr.h>
5#include <cpu/x86/cache.h>
6#include <cpu/x86/post_code.h>
7
8#define NoEvictMod_MSR 0x2e0
9
10.code32
11.global chipset_teardown_car
12
13chipset_teardown_car:
14 pop %esp
15
Yuchen He1e67adb2023-07-25 21:28:36 +0200[diff] [blame^]16 post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]17
18 /* Disable cache. */
19 movl %cr0, %eax
20 orl $CR0_CacheDisable, %eax
21 movl %eax, %cr0
22
Yuchen He1e67adb2023-07-25 21:28:36 +0200[diff] [blame^]23 post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]24
25 /* Disable MTRR. */
26 movl $MTRR_DEF_TYPE_MSR, %ecx
27 rdmsr
28 andl $(~MTRR_DEF_TYPE_EN), %eax
29 wrmsr
30
31 /* Disable the no eviction run state */
Elyes HAOUAS6d772bc2018-12-22 09:19:49 +0100[diff] [blame]32 movl $NoEvictMod_MSR, %ecx
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]33 rdmsr
Elyes HAOUAS6d772bc2018-12-22 09:19:49 +0100[diff] [blame]34 andl $~2, %eax
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]35 wrmsr
Elyes HAOUAS6d772bc2018-12-22 09:19:49 +0100[diff] [blame]36 andl $~1, %eax
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]37 wrmsr
38
Yuchen He1e67adb2023-07-25 21:28:36 +0200[diff] [blame^]39 post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
Arthur Heymansdd4d8952018-06-03 12:04:26 +0200[diff] [blame]40
41 /* Return to caller. */
42 jmp *%esp