Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #ifndef __SOC_NVIDIA_TEGRA_I2C_H__ |
| 17 | #define __SOC_NVIDIA_TEGRA_I2C_H__ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | |
| 21 | void i2c_init(unsigned bus); |
Julius Werner | 37d7ac8 | 2014-05-05 18:03:46 -0700 | [diff] [blame] | 22 | void tegra_software_i2c_init(unsigned bus); |
| 23 | void tegra_software_i2c_disable(unsigned bus); |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 24 | |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 25 | enum { |
| 26 | /* Word 0 */ |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 27 | IOHEADER_PROTHDRSZ_SHIFT = 28, |
| 28 | IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT, |
| 29 | IOHEADER_PKTID_SHIFT = 16, |
| 30 | IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT, |
| 31 | IOHEADER_CONTROLLER_ID_SHIFT = 12, |
| 32 | IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT, |
| 33 | IOHEADER_PROTOCOL_SHIFT = 4, |
| 34 | IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT, |
| 35 | IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT, |
| 36 | IOHEADER_PKTTYPE_SHIFT = 0, |
| 37 | IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT, |
| 38 | IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT, |
| 39 | IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT, |
| 40 | IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT, |
| 41 | IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT, |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 42 | |
| 43 | /* Word 1 */ |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 44 | IOHEADER_PAYLOADSIZE_SHIFT = 0, |
| 45 | IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | enum { |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 49 | IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25, |
| 50 | IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25, |
| 51 | IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25, |
| 52 | IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24, |
| 53 | IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22, |
| 54 | IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21, |
| 55 | IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20, |
| 56 | IOHEADER_I2C_REQ_READ = 0x1 << 19, |
| 57 | IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18, |
| 58 | IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18, |
| 59 | IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18, |
| 60 | IOHEADER_I2C_REQ_IE = 0x1 << 17, |
| 61 | IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16, |
| 62 | IOHEADER_I2C_REQ_STOP = 0x0 << 16, |
| 63 | IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15, |
| 64 | IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12, |
| 65 | IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK = |
| 66 | 0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT, |
| 67 | IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0, |
| 68 | IOHEADER_I2C_REQ_SLAVE_ADDR_MASK = |
| 69 | 0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | enum { |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 73 | I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15, |
| 74 | I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, |
| 75 | I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT, |
| 76 | I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11, |
| 77 | I2C_CNFG_PACKET_MODE_EN = 0x1 << 10, |
| 78 | I2C_CNFG_SEND = 0x1 << 9, |
| 79 | I2C_CNFG_NOACK = 0x1 << 8, |
| 80 | I2C_CNFG_CMD2 = 0x1 << 7, |
| 81 | I2C_CNFG_CMD1 = 0x1 << 6, |
| 82 | I2C_CNFG_START = 0x1 << 5, |
| 83 | I2C_CNFG_SLV2_SHIFT = 4, |
| 84 | I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT, |
| 85 | I2C_CNFG_LENGTH_SHIFT = 1, |
| 86 | I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT, |
| 87 | I2C_CNFG_A_MOD = 0x1 << 0, |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | enum { |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 91 | I2C_PKT_STATUS_COMPLETE = 0x1 << 24, |
| 92 | I2C_PKT_STATUS_PKT_ID_SHIFT = 16, |
| 93 | I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT, |
| 94 | I2C_PKT_STATUS_BYTENUM_SHIFT = 4, |
| 95 | I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT, |
| 96 | I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3, |
| 97 | I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2, |
| 98 | I2C_PKT_STATUS_ARB_LOST = 0x1 << 1, |
| 99 | I2C_PKT_STATUS_BUSY = 0x1 << 0 |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | enum { |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 103 | I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, |
| 104 | I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = |
| 105 | 0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, |
| 106 | I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, |
| 107 | I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = |
| 108 | 0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 109 | }; |
| 110 | |
Tom Warren | bb932c5 | 2014-04-30 14:51:38 -0700 | [diff] [blame] | 111 | enum { |
| 112 | I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16, |
| 113 | I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK = |
Tom Warren | 4a810ba | 2014-07-02 09:25:35 -0700 | [diff] [blame] | 114 | 0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, |
Tom Warren | bb932c5 | 2014-04-30 14:51:38 -0700 | [diff] [blame] | 115 | I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2, |
Tom Warren | 4a810ba | 2014-07-02 09:25:35 -0700 | [diff] [blame] | 116 | I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1, |
Tom Warren | bb932c5 | 2014-04-30 14:51:38 -0700 | [diff] [blame] | 117 | I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0, |
| 118 | |
| 119 | I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0, |
| 120 | |
| 121 | I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE = 0x1 << 0 |
| 122 | }; |
| 123 | |
Gabe Black | 6541b28 | 2014-03-26 21:43:53 -0700 | [diff] [blame] | 124 | struct tegra_i2c_bus_info { |
| 125 | void *base; |
| 126 | uint32_t reset_bit; |
| 127 | void (*reset_func)(u32 bit); |
| 128 | }; |
| 129 | |
| 130 | extern struct tegra_i2c_bus_info tegra_i2c_info[]; |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 131 | |
| 132 | struct tegra_i2c_regs { |
| 133 | uint32_t cnfg; |
| 134 | uint32_t cmd_addr0; |
| 135 | uint32_t cmd_addr1; |
| 136 | uint32_t cmd_data1; |
| 137 | uint32_t cmd_data2; |
| 138 | uint8_t _rsv0[8]; |
| 139 | uint32_t status; |
| 140 | uint32_t sl_cnfg; |
| 141 | uint32_t sl_rcvd; |
| 142 | uint32_t sl_status; |
| 143 | uint32_t sl_addr1; |
| 144 | uint32_t sl_addr2; |
| 145 | uint32_t tlow_sext; |
| 146 | uint8_t _rsv1[4]; |
| 147 | uint32_t sl_delay_count; |
| 148 | uint32_t sl_int_mask; |
| 149 | uint32_t sl_int_source; |
| 150 | uint32_t sl_int_set; |
| 151 | uint8_t _rsv2[4]; |
| 152 | uint32_t tx_packet_fifo; |
| 153 | uint32_t rx_fifo; |
| 154 | uint32_t packet_transfer_status; |
| 155 | uint32_t fifo_control; |
| 156 | uint32_t fifo_status; |
| 157 | uint32_t interrupt_mask; |
| 158 | uint32_t interrupt_status; |
| 159 | uint32_t clk_divisor; |
| 160 | uint32_t interrupt_source; |
| 161 | uint32_t interrupt_set; |
| 162 | uint32_t slv_tx_packet_fifo; |
| 163 | uint32_t slv_rx_fifo; |
| 164 | uint32_t slv_packet_status; |
| 165 | uint32_t bus_clear_config; |
| 166 | uint32_t bus_clear_status; |
Tom Warren | bb932c5 | 2014-04-30 14:51:38 -0700 | [diff] [blame] | 167 | uint32_t config_load; |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 168 | }; |
Tom Warren | bb932c5 | 2014-04-30 14:51:38 -0700 | [diff] [blame] | 169 | check_member(tegra_i2c_regs, config_load, 0x8C); |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 170 | |
Yen Lin | cb6bb3b | 2015-04-03 16:32:26 -0700 | [diff] [blame] | 171 | extern unsigned g_num_i2c_buses; |
| 172 | |
Gabe Black | 14eb43b | 2013-10-07 01:57:42 -0700 | [diff] [blame] | 173 | #endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */ |