blob: 1178031f8d5ef440c8a0968c2177b915306170f3 [file] [log] [blame]
Lee Leahy01728bb2016-07-20 08:58:58 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
5 * Copyright (C) 2015-2016 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <console/console.h>
17#include <fsp/util.h>
18#include <soc/ramstage.h>
19
Lee Leahy1e24bf32017-03-13 17:13:39 -070020void fsp_silicon_init(bool s3wake)
Lee Leahy01728bb2016-07-20 08:58:58 -070021{
22 if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
23 intel_silicon_init();
24 else
Lee Leahy1e24bf32017-03-13 17:13:39 -070025 fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
Lee Leahy01728bb2016-07-20 08:58:58 -070026}
27
28void soc_silicon_init_params(SILICON_INIT_UPD *upd)
29{
30}
31
32void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
33 SILICON_INIT_UPD *new)
34{
35}