soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c
new file mode 100644
index 0000000..ee10e38
--- /dev/null
+++ b/src/soc/intel/quark/fsp1_1.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/ramstage.h>
+
+void fsp_silicon_init(void)
+{
+ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
+ intel_silicon_init();
+ else
+ fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+}
+
+void soc_silicon_init_params(SILICON_INIT_UPD *upd)
+{
+}
+
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
+ SILICON_INIT_UPD *new)
+{
+}