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Patrick Georgi2efc8802012-11-06 11:03:53 +01001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Patrick Georgi2efc8802012-11-06 11:03:53 +010015
16config NORTHBRIDGE_INTEL_GM45
17 bool
18
19if NORTHBRIDGE_INTEL_GM45
20
21config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
22 def_bool y
23 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenko88010112014-08-16 03:35:33 +020024 select VGA
25 select INTEL_EDID
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010026 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010027 select INTEL_GMA_SSC_ALTERNATE_REF
Kyösti Mälkki122e5bc2016-07-22 22:53:19 +030028 select RELOCATABLE_RAMSTAGE
Patrick Georgi2efc8802012-11-06 11:03:53 +010029
Martin Roth59ff3402016-02-09 09:06:46 -070030config CBFS_SIZE
31 hex
32 default 0x100000
33
Kyösti Mälkki35a72492013-07-01 11:21:53 +030034config BOOTBLOCK_NORTHBRIDGE_INIT
35 string
36 default "northbridge/intel/gm45/bootblock.c"
37
Vladimir Serbinenkod668cce2014-08-10 21:58:23 +020038config VGA_BIOS_ID
39 string
40 default "8086,2a42"
41
Arthur Heymans1dcb2ac2017-05-10 13:11:11 +020042config MMCONF_BASE_ADDRESS
43 hex
44 default 0xf0000000
45
Patrick Georgi2efc8802012-11-06 11:03:53 +010046endif