Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | e28bd4a | 2013-09-07 11:38:56 +0300 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Nico Huber | 6760e0b | 2019-11-17 02:34:53 +0100 | [diff] [blame] | 5 | #include <cf9_reset.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 6 | #include <ip_checksum.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Kyösti Mälkki | f555a58 | 2020-01-06 19:41:42 +0200 | [diff] [blame] | 8 | #include <device/smbus_host.h> |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 9 | #include <southbridge/intel/common/gpio.h> |
| 10 | #include <southbridge/intel/common/pmbase.h> |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 11 | #include <southbridge/intel/common/rcba.h> |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 12 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 13 | /* For DMI bar. */ |
Elyes HAOUAS | 10b65dc | 2018-06-16 18:39:26 +0200 | [diff] [blame] | 14 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 15 | |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 16 | #include "pch.h" |
Arthur Heymans | 6beaef9 | 2019-06-16 23:29:23 +0200 | [diff] [blame] | 17 | #include "chip.h" |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 18 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 19 | #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
Patrick Rudolph | 873178b | 2023-10-02 07:06:45 +0200 | [diff] [blame] | 20 | #define PCI_DEVICE_ID_INTEL_UM77 0x1e58 |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 21 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 22 | static void wait_iobp(void) |
Kyösti Mälkki | e28bd4a | 2013-09-07 11:38:56 +0300 | [diff] [blame] | 23 | { |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 24 | while (RCBA8(IOBPS) & 1) |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 25 | ; // implement timeout? |
Kyösti Mälkki | e28bd4a | 2013-09-07 11:38:56 +0300 | [diff] [blame] | 26 | } |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 27 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 28 | static u32 read_iobp(u32 address) |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 29 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 30 | u32 ret; |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 31 | |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 32 | RCBA32(IOBPIRI) = address; |
| 33 | RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 34 | wait_iobp(); |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 35 | ret = RCBA32(IOBPD); |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 36 | wait_iobp(); |
Elyes HAOUAS | 3c3f836 | 2019-05-22 20:31:48 +0200 | [diff] [blame] | 37 | RCBA8(IOBPS); // call wait_iobp() instead here? |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 38 | return ret; |
| 39 | } |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 40 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 41 | static void write_iobp(u32 address, u32 val) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 42 | { |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 43 | /* this function was probably pch_iobp_update with the andvalue |
| 44 | * being 0. So either the IOBP read can be removed or this function |
| 45 | * and the pch_iobp_update function in ramstage could be merged */ |
| 46 | read_iobp(address); |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 47 | RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 48 | wait_iobp(); |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 49 | |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 50 | RCBA32(IOBPD) = val; |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 51 | wait_iobp(); |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 52 | RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; |
| 53 | |
Elyes HAOUAS | 3c3f836 | 2019-05-22 20:31:48 +0200 | [diff] [blame] | 54 | RCBA8(IOBPS); // call wait_iobp() instead here? |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 55 | } |
| 56 | |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 57 | void early_pch_init_native_dmi_pre(void) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 58 | { |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 59 | /* Link Capabilities Register */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 60 | RCBA32(LCAP) = (RCBA32(LCAP) & ~0x3fc00) | |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 61 | (3 << 10) | // L0s and L1 entry supported |
| 62 | (2 << 12) | // L0s 128 ns to less than 256 ns |
| 63 | (2 << 15); // L1 2 us to less than 4 us |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 64 | |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 65 | RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 66 | RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 67 | } |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 68 | |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 69 | void early_pch_init_native_dmi_post(void) |
| 70 | { |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 71 | RCBA32(CIR0); // !!! = 0x01200654 |
| 72 | RCBA32(CIR0) = 0x01200654; |
| 73 | RCBA32(CIR0); // !!! = 0x01200654 |
| 74 | RCBA32(CIR0) = 0x012a0654; |
| 75 | RCBA32(CIR0); // !!! = 0x012a0654 |
| 76 | RCBA8(UPDCR); // !!! = 0x00 |
| 77 | RCBA8(UPDCR) = 0x05; |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Virtual Channel resources must match settings in DMIBAR! |
| 81 | * |
| 82 | * Some of the following settings are taken from |
| 83 | * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel |
| 84 | * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and |
| 85 | * serialice traces. |
| 86 | */ |
| 87 | |
| 88 | /* Virtual Channel 0 Resource Control Register. |
| 89 | * Enable channel. |
| 90 | * Set Virtual Channel Identifier. |
| 91 | * Map TC0 and TC3 and TC4 to VC0. |
| 92 | */ |
| 93 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 94 | RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 95 | |
| 96 | /* Virtual Channel 1 Resource Control Register. |
| 97 | * Enable channel. |
| 98 | * Set Virtual Channel Identifier. |
| 99 | * Map TC1 and TC5 to VC1. |
| 100 | */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 101 | RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 102 | /* Read back register */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 103 | RCBA32(V1CTL); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 104 | |
| 105 | /* Virtual Channel private Resource Control Register. |
| 106 | * Enable channel. |
| 107 | * Set Virtual Channel Identifier. |
| 108 | * Map TC2 and TC6 to VCp. |
| 109 | */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 110 | RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 111 | /* Read back register */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 112 | RCBA32(CIR31); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 113 | |
| 114 | /* Virtual Channel ME Resource Control Register. |
| 115 | * Enable channel. |
| 116 | * Set Virtual Channel Identifier. |
| 117 | * Map TC7 to VCm. |
| 118 | */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 119 | RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 120 | |
| 121 | /* Lock Virtual Channel Resource control register. */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 122 | RCBA32(CIR0) |= TCLOCKDN; |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 123 | /* Read back register */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 124 | RCBA32(CIR0); |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 125 | |
| 126 | /* Wait for virtual channels negotiation pending */ |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 127 | while (RCBA16(V0STS) & VCNEGPND) |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 128 | ; |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 129 | while (RCBA16(V1STS) & VCNEGPND) |
Patrick Rudolph | bf74350 | 2019-03-25 17:05:20 +0100 | [diff] [blame] | 130 | ; |
| 131 | while (RCBA16(0x2036) & VCNEGPND) |
| 132 | ; |
| 133 | while (RCBA16(0x2046) & VCNEGPND) |
| 134 | ; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 135 | } |
| 136 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 137 | void early_pch_init_native(void) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 138 | { |
Patrick Rudolph | 873178b | 2023-10-02 07:06:45 +0200 | [diff] [blame] | 139 | const u16 dev_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); |
| 140 | u8 pcie_ports = (dev_id == PCI_DEVICE_ID_INTEL_UM77) ? 4 : 8; |
| 141 | |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 142 | pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 143 | |
Patrick Rudolph | 873178b | 2023-10-02 07:06:45 +0200 | [diff] [blame] | 144 | /* Clear this bit early for PCIe device detection */ |
| 145 | for (uint8_t i = 0; i < pcie_ports; i++) |
| 146 | pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0); |
| 147 | |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 148 | RCBA32(CIR1) = 0x00109000; |
| 149 | RCBA32(REC); // !!! = 0x00000000 |
| 150 | RCBA32(REC) = 0x40000000; |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 151 | RCBA32(0x100c) = 0x01110000; |
| 152 | RCBA8(0x2340) = 0x1b; |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 153 | RCBA32(CIR6); // !!! = 0x0a080000 |
| 154 | RCBA32(CIR6) = 0x0a280000; |
Elyes HAOUAS | 3c3f836 | 2019-05-22 20:31:48 +0200 | [diff] [blame] | 155 | RCBA32(0x2310); // !!! = 0xc809605b |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 156 | RCBA32(0x2310) = 0xa809605b; |
Patrick Rudolph | 4f8b108 | 2019-07-14 11:54:58 +0200 | [diff] [blame] | 157 | RCBA32(DMC2) = 0x00854c74; |
| 158 | RCBA8(RPC); // !!! = 0x00 |
Elyes HAOUAS | 3c3f836 | 2019-05-22 20:31:48 +0200 | [diff] [blame] | 159 | RCBA32(0x2310); // !!! = 0xa809605b |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 160 | RCBA32(0x2310) = 0xa809605b; |
Elyes HAOUAS | 3c3f836 | 2019-05-22 20:31:48 +0200 | [diff] [blame] | 161 | RCBA32(0x2310); // !!! = 0xa809605b |
Patrick Rudolph | a1e9eef | 2019-03-25 11:47:36 +0100 | [diff] [blame] | 162 | RCBA32(0x2310) = 0xa809605b; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 163 | |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 164 | write_iobp(0xea007f62, 0x00590133); |
| 165 | write_iobp(0xec007f62, 0x00590133); |
| 166 | write_iobp(0xec007f64, 0x59555588); |
| 167 | write_iobp(0xea0040b9, 0x0001051c); |
| 168 | write_iobp(0xeb0040a1, 0x800084ff); |
| 169 | write_iobp(0xec0040a1, 0x800084ff); |
| 170 | write_iobp(0xea004001, 0x00008400); |
| 171 | write_iobp(0xeb004002, 0x40201758); |
| 172 | write_iobp(0xec004002, 0x40201758); |
| 173 | write_iobp(0xea004002, 0x00601758); |
| 174 | write_iobp(0xea0040a1, 0x810084ff); |
| 175 | write_iobp(0xeb0040b1, 0x0001c598); |
| 176 | write_iobp(0xec0040b1, 0x0001c598); |
| 177 | write_iobp(0xeb0040b6, 0x0001c598); |
| 178 | write_iobp(0xea0000a9, 0x80ff969f); |
| 179 | write_iobp(0xea0001a9, 0x80ff969f); |
| 180 | write_iobp(0xeb0040b2, 0x0001c396); |
| 181 | write_iobp(0xeb0040b3, 0x0001c396); |
| 182 | write_iobp(0xec0040b2, 0x0001c396); |
| 183 | write_iobp(0xea0001a9, 0x80ff94ff); |
| 184 | write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f); |
| 185 | write_iobp(0xea0000a9, 0x80ff94ff); |
| 186 | write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 187 | |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 188 | write_iobp(0xea007f05, 0x00010642); |
| 189 | write_iobp(0xea0040b7, 0x0001c91c); |
| 190 | write_iobp(0xea0040b8, 0x0001c91c); |
| 191 | write_iobp(0xeb0040a1, 0x820084ff); |
| 192 | write_iobp(0xec0040a1, 0x820084ff); |
| 193 | write_iobp(0xea007f0a, 0xc2480000); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 194 | |
Felix Held | 2adab28 | 2017-07-29 16:48:10 +0200 | [diff] [blame] | 195 | write_iobp(0xec00404d, 0x1ff177f); |
| 196 | write_iobp(0xec000084, 0x5a600000); |
| 197 | write_iobp(0xec000184, 0x5a600000); |
| 198 | write_iobp(0xec000284, 0x5a600000); |
| 199 | write_iobp(0xec000384, 0x5a600000); |
| 200 | write_iobp(0xec000094, 0x000f0501); |
| 201 | write_iobp(0xec000194, 0x000f0501); |
| 202 | write_iobp(0xec000294, 0x000f0501); |
| 203 | write_iobp(0xec000394, 0x000f0501); |
| 204 | write_iobp(0xec000096, 0x00000001); |
| 205 | write_iobp(0xec000196, 0x00000001); |
| 206 | write_iobp(0xec000296, 0x00000001); |
| 207 | write_iobp(0xec000396, 0x00000001); |
| 208 | write_iobp(0xec000001, 0x00008c08); |
| 209 | write_iobp(0xec000101, 0x00008c08); |
| 210 | write_iobp(0xec000201, 0x00008c08); |
| 211 | write_iobp(0xec000301, 0x00008c08); |
| 212 | write_iobp(0xec0040b5, 0x0001c518); |
| 213 | write_iobp(0xec000087, 0x06077597); |
| 214 | write_iobp(0xec000187, 0x06077597); |
| 215 | write_iobp(0xec000287, 0x06077597); |
| 216 | write_iobp(0xec000387, 0x06077597); |
| 217 | write_iobp(0xea000050, 0x00bb0157); |
| 218 | write_iobp(0xea000150, 0x00bb0157); |
| 219 | write_iobp(0xec007f60, 0x77777d77); |
| 220 | write_iobp(0xea00008d, 0x01320000); |
| 221 | write_iobp(0xea00018d, 0x01320000); |
| 222 | write_iobp(0xec0007b2, 0x04514b5e); |
| 223 | write_iobp(0xec00078c, 0x40000200); |
| 224 | write_iobp(0xec000780, 0x02000020); |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 225 | } |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 226 | |
| 227 | static void pch_enable_bars(void) |
| 228 | { |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 229 | pci_write_config32(PCH_LPC_DEV, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 230 | |
| 231 | pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); |
| 232 | |
Angel Pons | f471171 | 2020-11-04 00:38:28 +0100 | [diff] [blame] | 233 | pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 234 | |
| 235 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); |
| 236 | |
| 237 | /* Enable GPIO functionality. */ |
| 238 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 239 | } |
| 240 | |
| 241 | static void pch_generic_setup(void) |
| 242 | { |
| 243 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 244 | write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ |
| 245 | } |
| 246 | |
Nico Huber | 6760e0b | 2019-11-17 02:34:53 +0100 | [diff] [blame] | 247 | static void pch_enable_gbe(void) |
| 248 | { |
| 249 | uint8_t wanted_buc; |
| 250 | |
| 251 | /* Don't do this in the bootblock, it might be RO. So one |
| 252 | couldn't change the setting later in an updated romstage. */ |
| 253 | if (ENV_BOOTBLOCK) |
| 254 | return; |
| 255 | |
| 256 | const struct device *const gbe = pcidev_on_root(0x19, 0); |
| 257 | if (gbe && gbe->enabled) |
| 258 | wanted_buc = RCBA8(BUC) & ~PCH_DISABLE_GBE; |
| 259 | else |
| 260 | wanted_buc = RCBA8(BUC) | PCH_DISABLE_GBE; |
| 261 | |
| 262 | if (RCBA8(BUC) != wanted_buc) { |
| 263 | RCBA8(BUC) = wanted_buc; |
| 264 | /* Be double sure not to reset for naught. */ |
| 265 | if (RCBA8(BUC) != wanted_buc) |
| 266 | return; |
| 267 | full_reset(); |
| 268 | } |
| 269 | } |
| 270 | |
Arthur Heymans | d28d507 | 2019-06-16 23:36:28 +0200 | [diff] [blame] | 271 | static void pch_enable_lpc_decode(void) |
Arthur Heymans | 6beaef9 | 2019-06-16 23:29:23 +0200 | [diff] [blame] | 272 | { |
Arthur Heymans | d28d507 | 2019-06-16 23:36:28 +0200 | [diff] [blame] | 273 | /* |
| 274 | * Enable some common LPC IO ranges: |
| 275 | * - 0x2e/0x2f, 0x4e/0x4f often SuperIO |
| 276 | * - 0x60/0x64, 0x62/0x66 often KBC/EC |
| 277 | * - 0x3f0-0x3f5/0x3f7 FDD |
| 278 | * - 0x378-0x37f and 0x778-0x77f LPT |
| 279 | * - 0x2f8-0x2ff COMB |
| 280 | * - 0x3f8-0x3ff COMA |
| 281 | */ |
| 282 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
Angel Pons | 6cd6e71 | 2020-05-07 00:54:42 +0200 | [diff] [blame] | 283 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN |
| 284 | | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); |
Arthur Heymans | d28d507 | 2019-06-16 23:36:28 +0200 | [diff] [blame] | 285 | |
Arthur Heymans | 6beaef9 | 2019-06-16 23:29:23 +0200 | [diff] [blame] | 286 | const struct device *dev = pcidev_on_root(0x1f, 0); |
| 287 | const struct southbridge_intel_bd82x6x_config *config = NULL; |
| 288 | |
| 289 | /* Set up generic decode ranges */ |
| 290 | if (!dev) |
| 291 | return; |
| 292 | if (dev->chip_info) |
| 293 | config = dev->chip_info; |
| 294 | if (!config) |
| 295 | return; |
| 296 | |
| 297 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); |
| 298 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); |
| 299 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); |
| 300 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); |
| 301 | } |
| 302 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 303 | __weak void mainboard_pch_lpc_setup(void) |
| 304 | { |
| 305 | } |
| 306 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 307 | void early_pch_init(void) |
| 308 | { |
Arthur Heymans | d28d507 | 2019-06-16 23:36:28 +0200 | [diff] [blame] | 309 | pch_enable_lpc_decode(); |
| 310 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 311 | mainboard_pch_lpc_setup(); |
Arthur Heymans | 6beaef9 | 2019-06-16 23:29:23 +0200 | [diff] [blame] | 312 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 313 | pch_enable_bars(); |
| 314 | |
| 315 | pch_generic_setup(); |
| 316 | |
Nico Huber | 6760e0b | 2019-11-17 02:34:53 +0100 | [diff] [blame] | 317 | pch_enable_gbe(); |
| 318 | |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 319 | setup_pch_gpios(&mainboard_gpio_map); |
Kyösti Mälkki | ffa520f | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 320 | |
Husni Faiz | f571ce5 | 2022-09-05 15:28:53 +0530 | [diff] [blame] | 321 | if (ENV_RAMINIT || (CONFIG(CONSOLE_I2C_SMBUS) && ENV_INITIAL_STAGE)) |
Kyösti Mälkki | ffa520f | 2020-01-07 12:00:31 +0200 | [diff] [blame] | 322 | enable_smbus(); |
Patrick Rudolph | 45d4b17 | 2019-03-24 12:27:31 +0100 | [diff] [blame] | 323 | } |