Blame - src/soc/amd/common/block/cpu/Kconfig - coreboot

blob: 0665e7d6f9620624eaf4edbae214517f1532d71f [file] [log] [blame]

Marshall Dawson	9df969a	2017-07-25 18:46:46 -0600	[diff] [blame]	1	config SOC_AMD_COMMON_BLOCK_CAR
				2	bool
Marshall Dawson	9df969a	2017-07-25 18:46:46 -0600	[diff] [blame]	3	help
				4	This option allows the SOC to use a standard AMD cache-as-ram (CAR)
Marshall Dawson	d61e832	2017-08-09 19:59:20 -0600	[diff] [blame]	5	implementation. CAR setup is built into bootblock and teardown is
				6	in postcar. The teardown procedure does not preserve the stack so
				7	it may not be appropriate for a romstage implementation without
				8	additional consideration. If this option is not used, the SOC must
				9	implement these functions separately.
Felix Held	befec1e	2020-11-06 00:26:03 +0100	[diff] [blame]	10	This is only used for AMD CPU before family 17h. From family 17h on
				11	the RAM is already initialized by the PSP before the x86 cores are
				12	released from reset.
Felix Held	9065f4f	2020-11-21 02:12:54 +0100	[diff] [blame]	13
				14	config SOC_AMD_COMMON_BLOCK_NONCAR
				15	bool
Felix Held	9065f4f	2020-11-21 02:12:54 +0100	[diff] [blame]	16	help
				17	From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
				18	more, since the RAM initialization is already done by the PSP when
				19	the x86 cores are released from reset.
				20
				21	if SOC_AMD_COMMON_BLOCK_NONCAR
				22
Arthur Heymans	4be0f4b	2022-03-30 23:08:21 +0200	[diff] [blame]	23	config BOOTBLOCK_IN_CBFS
				24	bool
				25	default n
				26
Felix Held	9065f4f	2020-11-21 02:12:54 +0100	[diff] [blame]	27	config MEMLAYOUT_LD_FILE
				28	string
				29	default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
				30
Raul E Rangel	55fea11	2021-07-23 16:43:18 -0600	[diff] [blame]	31	config CBFS_CACHE_SIZE
				32	hex
				33	help
				34	The size of the cbfs_cache region.
				35
Felix Held	9065f4f	2020-11-21 02:12:54 +0100	[diff] [blame]	36	endif # SOC_AMD_COMMON_BLOCK_NONCAR
Felix Held	2f5c759	2020-12-04 17:31:10 +0100	[diff] [blame]	37
Felix Held	1e1d490	2021-07-14 00:05:39 +0200	[diff] [blame]	38	config SOC_AMD_COMMON_BLOCK_MCA_COMMON
				39	bool
				40	help
				41	Add common machine check architecture support. Do not select this
				42	in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or
				43	SOC_AMD_COMMON_BLOCK_MCAX which will select this one.
				44
				45	config SOC_AMD_COMMON_BLOCK_MCA
				46	bool
				47	select SOC_AMD_COMMON_BLOCK_MCA_COMMON
				48	help
				49	Add IA32 machine check architecture (MCA) support for pre-Zen CPUs.
				50
				51	config SOC_AMD_COMMON_BLOCK_MCAX
				52	bool
				53	select SOC_AMD_COMMON_BLOCK_MCA_COMMON
				54	help
				55	Add extended machine check architecture (MCAX) support for AMD family
				56	17h, 19h and possibly newer CPUs.
				57
Felix Held	bc13481	2021-02-10 02:26:10 +0100	[diff] [blame]	58	config SOC_AMD_COMMON_BLOCK_SMM
				59	bool
Felix Held	bc13481	2021-02-10 02:26:10 +0100	[diff] [blame]	60	help
Felix Held	746f438	2021-02-16 17:42:56 +0100	[diff] [blame]	61	Add common SMM relocation, finalization and handler functionality to
				62	the build.
Felix Held	bc13481	2021-02-10 02:26:10 +0100	[diff] [blame]	63
Felix Held	2f5c759	2020-12-04 17:31:10 +0100	[diff] [blame]	64	config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
				65	bool
				66	select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function
				67	select TSC_SYNC_LFENCE
				68	select UDELAY_TSC
Felix Held	2f5c759	2020-12-04 17:31:10 +0100	[diff] [blame]	69	help
				70	Select this option to add the common functions for getting the TSC
				71	frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC-
				72	based monotonic timer functionality to the build.
Raul E Rangel	394c6b0	2021-02-12 14:37:43 -0700	[diff] [blame]	73
				74	config SOC_AMD_COMMON_BLOCK_UCODE
				75	bool
Raul E Rangel	394c6b0	2021-02-12 14:37:43 -0700	[diff] [blame]	76	help
				77	Builds in support for loading uCode.