Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | register "eist_enable" = "1" |
| 11 | |
| 12 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 13 | |
| 14 | # Set the Thermal Control Circuit (TCC) activation value to 95C |
| 15 | # even though FSP integration guide says to set it to 100C for SKL-U |
| 16 | # (offset at 0), because when the TCC activates at 100C, the CPU |
| 17 | # will have already shut itself down from overheating protection. |
| 18 | register "tcc_offset" = "5" # TCC of 95C |
| 19 | |
| 20 | # GPE configuration |
| 21 | # Note that GPE events called out in ASL code rely on this |
| 22 | # route. i.e. If this route changes then the affected GPE |
| 23 | # offset bits also need to be changed. |
| 24 | register "gpe0_dw0" = "GPP_C" |
| 25 | register "gpe0_dw1" = "GPP_D" |
| 26 | register "gpe0_dw2" = "GPP_E" |
| 27 | |
| 28 | register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f |
| 29 | register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef |
| 30 | register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 31 | |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 32 | # Disable DPTF |
| 33 | register "dptf_enable" = "0" |
| 34 | |
| 35 | # FSP Configuration |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 36 | register "SataSalpSupport" = "0" |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 37 | register "SataPortsEnable" = "{ |
| 38 | [0] = 1, |
| 39 | [1] = 1, |
| 40 | [2] = 1, |
| 41 | }" |
| 42 | register "SataPortsDevSlp" = "{ |
| 43 | [0] = 0, |
| 44 | [1] = 0, |
| 45 | [2] = 0, |
| 46 | }" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 47 | register "SataSpeedLimit" = "2" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 48 | register "DspEnable" = "1" |
| 49 | register "IoBufferOwnership" = "0" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 50 | register "SsicPortEnable" = "0" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 51 | register "ScsEmmcHs400Enabled" = "0" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 52 | register "SkipExtGfxScan" = "1" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 53 | register "SaGv" = "SaGv_Enabled" |
| 54 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 55 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 56 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 57 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 58 | |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 59 | # VR Settings Configuration for 4 Domains |
| 60 | #+----------------+-------+-------+-------------+-------+ |
| 61 | #| Domain/Setting | SA | IA | GT-Unsliced | GT | |
| 62 | #+----------------+-------+-------+-------------+-------+ |
| 63 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 64 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 65 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 66 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 67 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 68 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 69 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 70 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 71 | #+----------------+-------+-------+-------------+-------+ |
| 72 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 73 | .vr_config_enable = 1, |
| 74 | .psi1threshold = VR_CFG_AMP(20), |
| 75 | .psi2threshold = VR_CFG_AMP(4), |
| 76 | .psi3threshold = VR_CFG_AMP(1), |
| 77 | .psi3enable = 1, |
| 78 | .psi4enable = 1, |
| 79 | .imon_slope = 0x0, |
| 80 | .imon_offset = 0x0, |
| 81 | .voltage_limit = 1520, |
| 82 | }" |
| 83 | |
| 84 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 85 | .vr_config_enable = 1, |
| 86 | .psi1threshold = VR_CFG_AMP(20), |
| 87 | .psi2threshold = VR_CFG_AMP(5), |
| 88 | .psi3threshold = VR_CFG_AMP(1), |
| 89 | .psi3enable = 1, |
| 90 | .psi4enable = 1, |
| 91 | .imon_slope = 0x0, |
| 92 | .imon_offset = 0x0, |
| 93 | .voltage_limit = 1520, |
| 94 | }" |
| 95 | |
| 96 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 97 | .vr_config_enable = 1, |
| 98 | .psi1threshold = VR_CFG_AMP(20), |
| 99 | .psi2threshold = VR_CFG_AMP(5), |
| 100 | .psi3threshold = VR_CFG_AMP(1), |
| 101 | .psi3enable = 1, |
| 102 | .psi4enable = 1, |
| 103 | .imon_slope = 0x0, |
| 104 | .imon_offset = 0x0, |
| 105 | .voltage_limit = 1520, |
| 106 | }" |
| 107 | |
| 108 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 109 | .vr_config_enable = 1, |
| 110 | .psi1threshold = VR_CFG_AMP(20), |
| 111 | .psi2threshold = VR_CFG_AMP(5), |
| 112 | .psi3threshold = VR_CFG_AMP(1), |
| 113 | .psi3enable = 1, |
| 114 | .psi4enable = 1, |
| 115 | .imon_slope = 0x0, |
| 116 | .imon_offset = 0x0, |
| 117 | .voltage_limit = 1520, |
| 118 | }" |
| 119 | |
| 120 | register "PcieRpEnable[2]" = "1" |
| 121 | register "PcieRpEnable[3]" = "1" |
| 122 | register "PcieRpEnable[4]" = "1" |
| 123 | register "PcieRpEnable[8]" = "1" |
| 124 | register "PcieRpEnable[9]" = "1" |
| 125 | register "PcieRpEnable[10]" = "1" |
| 126 | register "PcieRpEnable[11]" = "1" |
| 127 | |
| 128 | register "PcieRpClkSrcNumber[0]" = "0" |
| 129 | register "PcieRpClkSrcNumber[3]" = "1" |
| 130 | register "PcieRpClkSrcNumber[4]" = "2" |
| 131 | register "PcieRpClkSrcNumber[8]" = "3" |
| 132 | register "PcieRpClkSrcNumber[9]" = "3" |
| 133 | register "PcieRpClkSrcNumber[10]" = "3" |
| 134 | register "PcieRpClkSrcNumber[11]" = "3" |
| 135 | |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 136 | register "usb2_ports" = "{ |
| 137 | [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ |
| 138 | [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ |
| 139 | [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ |
| 140 | [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ |
| 141 | [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ |
| 142 | [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ |
| 143 | [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ |
| 144 | [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ |
| 145 | }" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 146 | |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 147 | register "usb3_ports" = "{ |
| 148 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ |
| 149 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ |
| 150 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ |
| 151 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ |
| 152 | }" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 153 | |
| 154 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 155 | register "power_limits_config" = "{ |
| 156 | .tdp_pl2_override = 25, |
| 157 | }" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 158 | |
| 159 | # Send an extra VR mailbox command for the PS4 exit issue |
| 160 | register "SendVrMbxCmd" = "2" |
| 161 | |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 162 | device domain 0 on |
Felix Singer | c3ec144 | 2023-11-12 17:35:05 +0000 | [diff] [blame] | 163 | device ref igpu on end |
| 164 | device ref sa_thermal on end |
| 165 | device ref south_xhci on end |
| 166 | device ref south_xdci on end |
| 167 | device ref thermal on end |
| 168 | device ref heci1 on end |
| 169 | device ref sata on end |
| 170 | device ref pcie_rp3 on end |
| 171 | device ref pcie_rp5 on |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 172 | smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" |
| 173 | "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" |
| 174 | end |
Felix Singer | c3ec144 | 2023-11-12 17:35:05 +0000 | [diff] [blame] | 175 | device ref pcie_rp6 on end |
| 176 | device ref pcie_rp9 on |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 177 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 178 | "SSD_M.2 2242/2280" "SlotDataBusWidth4X" |
| 179 | end |
Felix Singer | c3ec144 | 2023-11-12 17:35:05 +0000 | [diff] [blame] | 180 | device ref pcie_rp10 on end |
| 181 | device ref pcie_rp11 on end |
| 182 | device ref pcie_rp12 on end |
| 183 | device ref lpc_espi on |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 184 | chip drivers/pc80/tpm |
| 185 | device pnp 0c31.0 on end |
| 186 | end |
| 187 | chip superio/ite/it8786e |
| 188 | register "TMPIN1.mode" = "THERMAL_PECI" |
| 189 | register "TMPIN1.offset" = "100" |
| 190 | register "TMPIN1.min" = "128" |
| 191 | register "TMPIN2.mode" = "THERMAL_RESISTOR" |
| 192 | register "TMPIN2.min" = "128" |
| 193 | register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" |
| 194 | register "ec.vin_mask" = "VIN_ALL" |
| 195 | # FAN1 is CPU fan (on board) |
| 196 | register "FAN1.mode" = "FAN_SMART_AUTOMATIC" |
| 197 | register "FAN1.smart.tmpin" = " 1" |
| 198 | register "FAN1.smart.tmp_off" = "35" |
| 199 | register "FAN1.smart.tmp_start" = "60" |
| 200 | register "FAN1.smart.tmp_full" = "85" |
| 201 | register "FAN1.smart.tmp_delta" = " 2" |
| 202 | register "FAN1.smart.pwm_start" = "20" |
| 203 | register "FAN1.smart.slope" = "24" |
| 204 | # FAN2 is system fan (4 pin connector populated) |
| 205 | #register "FAN2.mode" = "FAN_MODE_OFF" |
| 206 | # FAN3 PWM is used for LVDS backlight control |
| 207 | #register "FAN3.mode" = "FAN_MODE_OFF" |
| 208 | |
| 209 | device pnp 2e.1 on # COM 1 |
| 210 | io 0x60 = 0x3f8 |
| 211 | irq 0x70 = 4 |
| 212 | end |
| 213 | device pnp 2e.2 on # COM 2 |
| 214 | io 0x60 = 0x2f8 |
| 215 | irq 0x70 = 3 |
| 216 | end |
| 217 | device pnp 2e.3 on # Printer Port |
| 218 | io 0x60 = 0x378 |
| 219 | io 0x62 = 0x778 |
| 220 | irq 0x70 = 5 |
| 221 | drq 0x74 = 3 |
| 222 | end |
| 223 | device pnp 2e.4 on # Environment Controller |
| 224 | io 0x60 = 0xa40 |
| 225 | io 0x62 = 0xa30 |
| 226 | irq 0x70 = 9 |
| 227 | end |
| 228 | device pnp 2e.5 on # Keyboard |
| 229 | io 0x60 = 0x60 |
| 230 | io 0x62 = 0x64 |
| 231 | irq 0x70 = 1 |
| 232 | end |
| 233 | device pnp 2e.6 on # Mouse |
| 234 | irq 0x70 = 12 |
| 235 | end |
| 236 | device pnp 2e.7 off # GPIO |
| 237 | end |
| 238 | device pnp 2e.8 on # COM 3 |
| 239 | io 0x60 = 0x3e8 |
| 240 | irq 0x70 = 3 |
| 241 | end |
| 242 | device pnp 2e.9 on # COM 4 |
| 243 | io 0x60 = 0x2e8 |
| 244 | irq 0x70 = 4 |
| 245 | end |
| 246 | device pnp 2e.a off end # CIR |
| 247 | device pnp 2e.b on # COM 5 |
| 248 | io 0x60 = 0x2f0 |
| 249 | irq 0x70 = 3 |
| 250 | end |
| 251 | device pnp 2e.c on # COM 6 |
| 252 | io 0x60 = 0x2e0 |
| 253 | irq 0x70 = 4 |
| 254 | end |
| 255 | end |
Felix Singer | c3ec144 | 2023-11-12 17:35:05 +0000 | [diff] [blame] | 256 | end |
| 257 | device ref hda on end |
| 258 | device ref smbus on end |
| 259 | device ref fast_spi on end |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 260 | end |
| 261 | end |