Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "0" |
| 5 | register "deep_s3_enable_dc" = "0" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_WAKE_PIN" |
| 9 | |
| 10 | register "eist_enable" = "1" |
| 11 | |
| 12 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 13 | |
| 14 | # Set the Thermal Control Circuit (TCC) activation value to 95C |
| 15 | # even though FSP integration guide says to set it to 100C for SKL-U |
| 16 | # (offset at 0), because when the TCC activates at 100C, the CPU |
| 17 | # will have already shut itself down from overheating protection. |
| 18 | register "tcc_offset" = "5" # TCC of 95C |
| 19 | |
| 20 | # GPE configuration |
| 21 | # Note that GPE events called out in ASL code rely on this |
| 22 | # route. i.e. If this route changes then the affected GPE |
| 23 | # offset bits also need to be changed. |
| 24 | register "gpe0_dw0" = "GPP_C" |
| 25 | register "gpe0_dw1" = "GPP_D" |
| 26 | register "gpe0_dw2" = "GPP_E" |
| 27 | |
| 28 | register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f |
| 29 | register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef |
| 30 | register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff |
| 31 | register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f |
| 32 | |
| 33 | # Enable "Intel Speed Shift Technology" |
| 34 | register "speed_shift_enable" = "1" |
| 35 | |
| 36 | # Disable DPTF |
| 37 | register "dptf_enable" = "0" |
| 38 | |
| 39 | # FSP Configuration |
| 40 | register "ProbelessTrace" = "0" |
| 41 | register "EnableLan" = "0" |
| 42 | register "EnableSata" = "1" |
| 43 | register "SataSalpSupport" = "0" |
| 44 | register "SataMode" = "0" |
| 45 | register "SataPortsEnable[0]" = "1" |
| 46 | register "SataPortsEnable[1]" = "1" |
| 47 | register "SataPortsEnable[2]" = "1" |
| 48 | register "SataPortsDevSlp[0]" = "0" |
| 49 | register "SataPortsDevSlp[1]" = "0" |
| 50 | register "SataPortsDevSlp[2]" = "0" |
| 51 | register "SataSpeedLimit" = "2" |
| 52 | register "EnableAzalia" = "1" |
| 53 | register "DspEnable" = "1" |
| 54 | register "IoBufferOwnership" = "0" |
| 55 | register "EnableTraceHub" = "0" |
| 56 | register "SsicPortEnable" = "0" |
| 57 | register "SmbusEnable" = "1" |
| 58 | register "Cio2Enable" = "0" |
| 59 | register "ScsEmmcEnabled" = "0" |
| 60 | register "ScsEmmcHs400Enabled" = "0" |
| 61 | register "ScsSdCardEnabled" = "0" |
| 62 | register "SkipExtGfxScan" = "1" |
| 63 | register "Device4Enable" = "1" |
| 64 | register "HeciEnabled" = "1" |
| 65 | register "SaGv" = "SaGv_Enabled" |
| 66 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 67 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 68 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 69 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 70 | register "PmTimerDisabled" = "1" |
| 71 | |
| 72 | register "pirqa_routing" = "PCH_IRQ11" |
| 73 | register "pirqb_routing" = "PCH_IRQ10" |
| 74 | register "pirqc_routing" = "PCH_IRQ11" |
| 75 | register "pirqd_routing" = "PCH_IRQ11" |
| 76 | register "pirqe_routing" = "PCH_IRQ11" |
| 77 | register "pirqf_routing" = "PCH_IRQ11" |
| 78 | register "pirqg_routing" = "PCH_IRQ11" |
| 79 | register "pirqh_routing" = "PCH_IRQ11" |
| 80 | |
| 81 | # VR Settings Configuration for 4 Domains |
| 82 | #+----------------+-------+-------+-------------+-------+ |
| 83 | #| Domain/Setting | SA | IA | GT-Unsliced | GT | |
| 84 | #+----------------+-------+-------+-------------+-------+ |
| 85 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 86 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 87 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 88 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 89 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 90 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 91 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 92 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 93 | #+----------------+-------+-------+-------------+-------+ |
| 94 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 95 | .vr_config_enable = 1, |
| 96 | .psi1threshold = VR_CFG_AMP(20), |
| 97 | .psi2threshold = VR_CFG_AMP(4), |
| 98 | .psi3threshold = VR_CFG_AMP(1), |
| 99 | .psi3enable = 1, |
| 100 | .psi4enable = 1, |
| 101 | .imon_slope = 0x0, |
| 102 | .imon_offset = 0x0, |
| 103 | .voltage_limit = 1520, |
| 104 | }" |
| 105 | |
| 106 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 107 | .vr_config_enable = 1, |
| 108 | .psi1threshold = VR_CFG_AMP(20), |
| 109 | .psi2threshold = VR_CFG_AMP(5), |
| 110 | .psi3threshold = VR_CFG_AMP(1), |
| 111 | .psi3enable = 1, |
| 112 | .psi4enable = 1, |
| 113 | .imon_slope = 0x0, |
| 114 | .imon_offset = 0x0, |
| 115 | .voltage_limit = 1520, |
| 116 | }" |
| 117 | |
| 118 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 119 | .vr_config_enable = 1, |
| 120 | .psi1threshold = VR_CFG_AMP(20), |
| 121 | .psi2threshold = VR_CFG_AMP(5), |
| 122 | .psi3threshold = VR_CFG_AMP(1), |
| 123 | .psi3enable = 1, |
| 124 | .psi4enable = 1, |
| 125 | .imon_slope = 0x0, |
| 126 | .imon_offset = 0x0, |
| 127 | .voltage_limit = 1520, |
| 128 | }" |
| 129 | |
| 130 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 131 | .vr_config_enable = 1, |
| 132 | .psi1threshold = VR_CFG_AMP(20), |
| 133 | .psi2threshold = VR_CFG_AMP(5), |
| 134 | .psi3threshold = VR_CFG_AMP(1), |
| 135 | .psi3enable = 1, |
| 136 | .psi4enable = 1, |
| 137 | .imon_slope = 0x0, |
| 138 | .imon_offset = 0x0, |
| 139 | .voltage_limit = 1520, |
| 140 | }" |
| 141 | |
| 142 | register "PcieRpEnable[2]" = "1" |
| 143 | register "PcieRpEnable[3]" = "1" |
| 144 | register "PcieRpEnable[4]" = "1" |
| 145 | register "PcieRpEnable[8]" = "1" |
| 146 | register "PcieRpEnable[9]" = "1" |
| 147 | register "PcieRpEnable[10]" = "1" |
| 148 | register "PcieRpEnable[11]" = "1" |
| 149 | |
| 150 | register "PcieRpClkSrcNumber[0]" = "0" |
| 151 | register "PcieRpClkSrcNumber[3]" = "1" |
| 152 | register "PcieRpClkSrcNumber[4]" = "2" |
| 153 | register "PcieRpClkSrcNumber[8]" = "3" |
| 154 | register "PcieRpClkSrcNumber[9]" = "3" |
| 155 | register "PcieRpClkSrcNumber[10]" = "3" |
| 156 | register "PcieRpClkSrcNumber[11]" = "3" |
| 157 | |
| 158 | |
| 159 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) |
| 160 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) |
| 161 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # WiFi |
| 162 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header |
| 163 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F_USB3 header |
| 164 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) |
| 165 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) |
| 166 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # GL850G for F_USB1 and F_USB2 headers |
| 167 | |
| 168 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) |
| 169 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) |
| 170 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header |
| 171 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header |
| 172 | |
| 173 | # PL2 override 25W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame^] | 174 | register "power_limits_config" = "{ |
| 175 | .tdp_pl2_override = 25, |
| 176 | }" |
Michał Żygowski | b9f9f6c | 2018-12-21 12:23:27 +0100 | [diff] [blame] | 177 | |
| 178 | # Send an extra VR mailbox command for the PS4 exit issue |
| 179 | register "SendVrMbxCmd" = "2" |
| 180 | |
| 181 | # Lock Down |
| 182 | register "common_soc_config" = "{ |
| 183 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 184 | }" |
| 185 | |
| 186 | device cpu_cluster 0 on |
| 187 | device lapic 0 on end |
| 188 | end |
| 189 | device domain 0 on |
| 190 | device pci 00.0 on end # Host Bridge |
| 191 | device pci 02.0 on end # Integrated Graphics Device |
| 192 | device pci 14.0 on end # USB xHCI |
| 193 | device pci 14.1 on end # USB xDCI (OTG) |
| 194 | device pci 14.2 on end # Thermal Subsystem |
| 195 | device pci 16.0 on end # Management Engine Interface 1 |
| 196 | device pci 16.1 off end # Management Engine Interface 2 |
| 197 | device pci 16.2 off end # Management Engine IDE-R |
| 198 | device pci 16.3 off end # Management Engine KT Redirection |
| 199 | device pci 16.4 off end # Management Engine Interface 3 |
| 200 | device pci 17.0 on end # SATA |
| 201 | device pci 1c.0 off end # PCI Express Port 1 |
| 202 | device pci 1c.1 off end # PCI Express Port 2 |
| 203 | device pci 1c.2 on end # PCI Express Port 3 |
| 204 | device pci 1c.3 off end # PCI Express Port 4 |
| 205 | device pci 1c.4 on # PCI Express Port 5 |
| 206 | smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" |
| 207 | "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" |
| 208 | end |
| 209 | device pci 1c.5 on end # PCI Express Port 6 |
| 210 | device pci 1c.6 off end # PCI Express Port 7 |
| 211 | device pci 1c.7 off end # PCI Express Port 8 |
| 212 | device pci 1d.0 on # PCI Express Port 9 |
| 213 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 214 | "SSD_M.2 2242/2280" "SlotDataBusWidth4X" |
| 215 | end |
| 216 | device pci 1d.1 on end # PCI Express Port 10 |
| 217 | device pci 1d.2 on end # PCI Express Port 11 |
| 218 | device pci 1d.3 on end # PCI Express Port 12 |
| 219 | device pci 1f.0 on |
| 220 | chip drivers/pc80/tpm |
| 221 | device pnp 0c31.0 on end |
| 222 | end |
| 223 | chip superio/ite/it8786e |
| 224 | register "TMPIN1.mode" = "THERMAL_PECI" |
| 225 | register "TMPIN1.offset" = "100" |
| 226 | register "TMPIN1.min" = "128" |
| 227 | register "TMPIN2.mode" = "THERMAL_RESISTOR" |
| 228 | register "TMPIN2.min" = "128" |
| 229 | register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" |
| 230 | register "ec.vin_mask" = "VIN_ALL" |
| 231 | # FAN1 is CPU fan (on board) |
| 232 | register "FAN1.mode" = "FAN_SMART_AUTOMATIC" |
| 233 | register "FAN1.smart.tmpin" = " 1" |
| 234 | register "FAN1.smart.tmp_off" = "35" |
| 235 | register "FAN1.smart.tmp_start" = "60" |
| 236 | register "FAN1.smart.tmp_full" = "85" |
| 237 | register "FAN1.smart.tmp_delta" = " 2" |
| 238 | register "FAN1.smart.pwm_start" = "20" |
| 239 | register "FAN1.smart.slope" = "24" |
| 240 | # FAN2 is system fan (4 pin connector populated) |
| 241 | #register "FAN2.mode" = "FAN_MODE_OFF" |
| 242 | # FAN3 PWM is used for LVDS backlight control |
| 243 | #register "FAN3.mode" = "FAN_MODE_OFF" |
| 244 | |
| 245 | device pnp 2e.1 on # COM 1 |
| 246 | io 0x60 = 0x3f8 |
| 247 | irq 0x70 = 4 |
| 248 | end |
| 249 | device pnp 2e.2 on # COM 2 |
| 250 | io 0x60 = 0x2f8 |
| 251 | irq 0x70 = 3 |
| 252 | end |
| 253 | device pnp 2e.3 on # Printer Port |
| 254 | io 0x60 = 0x378 |
| 255 | io 0x62 = 0x778 |
| 256 | irq 0x70 = 5 |
| 257 | drq 0x74 = 3 |
| 258 | end |
| 259 | device pnp 2e.4 on # Environment Controller |
| 260 | io 0x60 = 0xa40 |
| 261 | io 0x62 = 0xa30 |
| 262 | irq 0x70 = 9 |
| 263 | end |
| 264 | device pnp 2e.5 on # Keyboard |
| 265 | io 0x60 = 0x60 |
| 266 | io 0x62 = 0x64 |
| 267 | irq 0x70 = 1 |
| 268 | end |
| 269 | device pnp 2e.6 on # Mouse |
| 270 | irq 0x70 = 12 |
| 271 | end |
| 272 | device pnp 2e.7 off # GPIO |
| 273 | end |
| 274 | device pnp 2e.8 on # COM 3 |
| 275 | io 0x60 = 0x3e8 |
| 276 | irq 0x70 = 3 |
| 277 | end |
| 278 | device pnp 2e.9 on # COM 4 |
| 279 | io 0x60 = 0x2e8 |
| 280 | irq 0x70 = 4 |
| 281 | end |
| 282 | device pnp 2e.a off end # CIR |
| 283 | device pnp 2e.b on # COM 5 |
| 284 | io 0x60 = 0x2f0 |
| 285 | irq 0x70 = 3 |
| 286 | end |
| 287 | device pnp 2e.c on # COM 6 |
| 288 | io 0x60 = 0x2e0 |
| 289 | irq 0x70 = 4 |
| 290 | end |
| 291 | end |
| 292 | end # LPC Interface |
| 293 | device pci 1f.1 on end # P2SB |
| 294 | device pci 1f.2 on end # Power Management Controller |
| 295 | device pci 1f.3 on end # Intel HDA |
| 296 | device pci 1f.4 on end # SMBus |
| 297 | device pci 1f.5 on end # PCH SPI |
| 298 | device pci 1f.6 off end # GbE |
| 299 | end |
| 300 | end |