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review.coreboot.org / coreboot / 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 / . / src / vendorcode / amd / cimx / sb800 / SB800.h
blob: 861a770c4e616de3b94550409ca7cfda359d7db6 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]1/*
2 *****************************************************************************
3 *
4 * Copyright (c) 2011, Advanced Micro Devices, Inc.
5 * All rights reserved.
Edward O'Callaghanb9a67002014-07-06 19:29:03 +1000[diff] [blame]6 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
Edward O'Callaghanb9a67002014-07-06 19:29:03 +1000[diff] [blame]14 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
15 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]16 * from this software without specific prior written permission.
Edward O'Callaghanb9a67002014-07-06 19:29:03 +1000[diff] [blame]17 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghanb9a67002014-07-06 19:29:03 +1000[diff] [blame]28 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame]29 * ***************************************************************************
30 *
31 */
32
33#pragma pack (push, 1)
34
35#define CIMX_SB_REVISION "1.1.0.6"
36#define CIMX_SB_ID "SB80A13"
37#ifndef SBCIMx_Version
38 #define SBCIMx_Version 0x1106
39#endif //CIMx_Version
40
41
42/*--------------------------- Documentation Pages ---------------------------*/
43/**
44 * @page SB_POWERON_INIT_Page SB_POWERON_INIT
45 * @section SB_POWERON_INIT Interface Call
46 * Initialize structure referenced by AMDSBCFG to default recommended value.
47 * @subsection SB_POWERON_INIT_CallIn Call Prototype
48 * @par
49 * sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface)
50 * @subsection SB_BEFORE_PCI_INIT_CallID Service ID
51 * @par
52 * <TABLE border="0">
53 * <TR><TD class="indexkey" width=380> SB_POWERON_INIT --> 0x00010001 </TD></TR>
54 * </TABLE>
55 * @subsection SB_POWERON_INIT_CallOut Prepare for Callout
56 * @par
57 * Not Applicable (Not necessary for the current implementation)
58 * @subsection SB_POWERON_INIT_Config Prepare for Configuration Data.
59 * @par
60 * <TABLE border="0">
61 * <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR>
62 * <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR>
63 * <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR>
64 * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
65 * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
66 * <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
67 * <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
68 * <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
69 * <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
70 * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
71 * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
72 * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
73 * <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
74 * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
75 * <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
76 * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
77 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
78 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
79 * </TABLE>
80 *
81 */
82#define SB_POWERON_INIT 0x00010001
83#define OUTDEBUG_PORT 0x00010002
84/*--------------------------- Documentation Pages ---------------------------*/
85/**
86 * @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT
87 * @section SB_BEFORE_PCI_INIT Interface Call
88 * Initialize structure referenced by AMDSBCFG to default recommended value.
89 * @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype
90 * @par
91 * sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
92 * @subsection SB_BEFORE_PCI_INIT_CallID Service ID
93 * @par
94 * <TABLE border="0">
95 * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT --> 0x00010010 </TD></TR>
96 * </TABLE>
97 * @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout
98 * @par
99 * <TABLE border="0">
100 * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
101 * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
102 * </TABLE>
103 * @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data.
104 * @par
105 * <TABLE border="0">
106 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
107 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
108 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
109 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
110 * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
111 * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
112 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
113 * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
114 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
115 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
116 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
117 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
118 * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
119 * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
120 * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
121 * </TABLE>
122 *
123 */
124#define SB_BEFORE_PCI_INIT 0x00010010
125/*--------------------------- Documentation Pages ---------------------------*/
126/**
127 * @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT
128 * @section SB_AFTER_PCI_INIT Interface Call
129 * Initialize structure referenced by AMDSBCFG to default recommended value.
130 * @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype
131 * @par
132 * sbAfterPciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
133 * @subsection SB_AFTER_PCI_INIT_CallID Service ID
134 * @par
135 * <TABLE border="0">
136 * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR>
137 * </TABLE>
138 * @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout
139 * @par
140 * Not Applicable (Not necessary for the current implementation)
141 * @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data.
142 * @par
143 * <TABLE border="0">
144 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
145 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
146 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
147 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
148 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
149 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
150 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
151 * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
152 * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
153 * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
154 * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
155 * </TABLE>
156 *
157 */
158#define SB_AFTER_PCI_INIT 0x00010020
159/*--------------------------- Documentation Pages ---------------------------*/
160/**
161 * @page SB_MID_POST_INIT_Page SB_MID_POST_INIT
162 * @section SB_MID_POST_INIT Interface Call
163 * Initialize structure referenced by AMDSBCFG to default recommended value.
164 * @subsection SB_MID_POST_INIT_CallIn Call Prototype
165 * @par
166 * sbMidPostInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
167 * @subsection SB_MID_POST_INIT_CallID Service ID
168 * @par
169 * <TABLE border="0">
170 * <TR><TD class="indexkey" width=380> SB_MID_POST_INIT --> 0x00010021 </TD></TR>
171 * </TABLE>
172 * @subsection SB_MID_POST_INIT_CallOut Prepare for Callout
173 * @par
174 * Not Applicable (Not necessary for the current implementation)
175 * @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data.
176 * @par
177 * <TABLE border="0">
178 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
179 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
180 * </TABLE>
181 *
182 */
183#define SB_MID_POST_INIT 0x00010021
184/*--------------------------- Documentation Pages ---------------------------*/
185/**
186 * @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT
187 * @section SB_LATE_POST_INIT Interface Call
188 * Initialize structure referenced by AMDSBCFG to default recommended value.
189 * @subsection SB_LATE_POST_INIT_CallIn Call Prototype
190 * @par
191 * sbLatePost ((AMDSBCFG*)pConfig) (Followed PH Interface)
192 * @subsection SB_LATE_POST_INIT_CallID Service ID
193 * @par
194 * <TABLE border="0">
195 * <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT --> 0x00010030 </TD></TR>
196 * </TABLE>
197 * @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout
198 * @par
199 * Not Applicable (Not necessary for the current implementation)
200 * @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data.
201 * @par
202 * <TABLE border="0">
203 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
204 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
205 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
206 * </TABLE>
207 *
208 */
209#define SB_LATE_POST_INIT 0x00010030
210/*--------------------------- Documentation Pages ---------------------------*/
211/**
212 * @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT
213 * @section SB_BEFORE_PCI_RESTORE_INIT Interface Call
214 * Initialize structure referenced by AMDSBCFG to default recommended value.
215 * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype
216 * @par
217 * sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
218 * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID
219 * @par
220 * <TABLE border="0">
221 * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT --> 0x00010040 </TD></TR>
222 * </TABLE>
223 * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout
224 * @par
225 * <TABLE border="0">
226 * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>
227 * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>
228 * </TABLE>
229 * @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
230 * @par
231 * <TABLE border="0">
232 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
233 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
234 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
235 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
236 * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
237 * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>
238 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
239 * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>
240 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
241 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
242 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
243 * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
244 * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
245 * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
246 * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
247 * </TABLE>
248 *
249 */
250#define SB_BEFORE_PCI_RESTORE_INIT 0x00010040
251/*--------------------------- Documentation Pages ---------------------------*/
252/**
253 * @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT
254 * @section SB_AFTER_PCI_RESTORE_INIT Interface Call
255 * Initialize structure referenced by AMDSBCFG to default recommended value.
256 * @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype
257 * @par
258 * sbAfterPciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)
259 * @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID
260 * @par
261 * <TABLE border="0">
262 * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT --> 0x00010050 </TD></TR>
263 * </TABLE>
264 * @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout
265 * @par
266 * Not Applicable (Not necessary for the current implementation)
267 * @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data.
268 * @par
269 * <TABLE border="0">
270 * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
271 * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>
272 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>
273 * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>
274 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>
275 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>
276 * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>
277 * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
278 * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
279 * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
280 * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>
281 * </TABLE>
282 *
283 */
284#define SB_AFTER_PCI_RESTORE_INIT 0x00010050
285/*--------------------------- Documentation Pages ---------------------------*/
286/**
287 * @page SB_SMM_SERVICE_Page SB_SMM_SERVICE
288 * @section SB_SMM_SERVICE Interface Call
289 * Initialize structure referenced by AMDSBCFG to default recommended value.
290 * @subsection SB_SMM_SERVICE_CallIn Call Prototype
291 * @par
292 * sbSmmService ((AMDSBCFG*)pConfig) (Followed PH Interface)
293 * @subsection SB_SMM_SERVICE_CallID Service ID
294 * @par
295 * <TABLE border="0">
296 * <TR><TD class="indexkey" width=380> SB_SMM_SERVICE --> 0x00010060 </TD></TR>
297 * </TABLE>
298 * @subsection SB_SMM_SERVICE_CallOut Prepare for Callout
299 * @par
300 * Not Applicable (Not necessary for the current implementation)
301 * @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data.
302 * @par
303 * Not necessary on current implementation
304 *
305 */
306#define SB_SMM_SERVICE 0x00010060
307/*--------------------------- Documentation Pages ---------------------------*/
308/**
309 * @page SB_SMM_ACPION_Page SB_SMM_ACPION
310 * @section SB_SMM_ACPION Interface Call
311 * Initialize structure referenced by AMDSBCFG to default recommended value.
312 * @subsection SB_SMM_ACPION_CallIn Call Prototype
313 * @par
314 * sbSmmAcpiOn ((AMDSBCFG*)pConfig) (Followed PH Interface)
315 * @subsection SB_SMM_ACPION_CallID Service ID
316 * @par
317 * <TABLE border="0">
318 * <TR><TD class="indexkey" width=380> SB_SMM_ACPION --> 0x00010061 </TD></TR>
319 * </TABLE>
320 * @subsection SB_SMM_ACPION_CallOut Prepare for Callout
321 * @par
322 * Not Applicable (Not necessary for the current implementation)
323 * @subsection SB_SMM_ACPION_Config Prepare for Configuration Data.
324 * @par
325 * Not necessary on current implementation
326 *
327 */
328#define SB_SMM_ACPION 0x00010061
329#define SB_EC_FANCONTROL 0x00010070
330
331#ifndef OEM_CALLBACK_BASE
332 #define OEM_CALLBACK_BASE 0x00010100
333#endif
334
335//0x00 - 0x0F callback functions are reserved for bootblock
336#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
337#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
338/*--------------------------- Documentation Pages ---------------------------*/
339/**
340 * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
341 * @section CB_SBGPP_RESET_ASSERT Interface Call
342 * Initialize structure referenced by AMDSBCFG to default recommended value.
343 * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
344 * @par
345 * <TABLE border="0">
346 * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
347 * </TABLE>
348 * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
349 * @par
350 * Not necessary on current implementation
351 *
352 */
353#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
354/*--------------------------- Documentation Pages ---------------------------*/
355/**
356 * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
357 * @section CB_SBGPP_RESET_DEASSERT Interface Call
358 * Initialize structure referenced by AMDSBCFG to default recommended value.
359 * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
360 * @par
361 * <TABLE border="0">
362 * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
363 * </TABLE>
364 * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
365 * @par
366 * Not necessary on current implementation
367 *
368 */
369#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
370
371#define IMC_FIRMWARE_FAIL OEM_CALLBACK_BASE + 0x40
372
373#define CFG_ADDR_PORT 0xCF8
374#define CFG_DATA_PORT 0xCFC
375
376#define ALINK_ACCESS_INDEX 0x0CD8
377#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
378
379/*------------------------------------------------------------------
380; I/O Base Address - Should be set by host BIOS
381;------------------------------------------------------------------ */
382#define DELAY_PORT 0x0E0
383
384/*------------------------------------------------------------------
385; Fuse ID and minor ID of efuse bits
386;------------------------------------------------------------------ */
387#define FUSE_ID_EFUSE_LOC 0x1F // efuse bits 248-255
388#define MINOR_ID_EFUSE_LOC 0x1E // efuse bits 240-247
389#define M1_D1_FUSE_ID 0x70
390#define M1_MINOR_ID 0x02
391
392/*------------------------------------------------------------------
393; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
394;------------------------------------------------------------------ */
395// ASIC VendorID and DeviceIDs
396#define AMD_SB_VID 0x1002
397#define SB_DEVICE_ID 0x4385 /* AMD ER SB800 */
398#define V_SB_SATA_VID AMD_SB_VID // dev 17 Func 0
399#define V_SB_SATA_DID 0x4390
400#define V_SB_SATA_AHCI_DID 0x4391
401#define V_SB_SATA_RAID_DID 0x4392
402#define V_SB_SATA_RAID5_DID 0x4393
403#define V_SB_USB_OHCI_VID AMD_SB_VID // dev 18 Func 0, dev 19 Func 0, dev 22 Func 0
404#define V_SB_USB_OHCI_DID 0x4397
405#define V_SB_USB_EHCI_VID AMD_SB_VID // dev 18 Func 2, dev 19 Func 2, dev 22 Func 2
406#define V_SB_USB_EHCI_DID 0x4396
407#define V_SB_SMBUS_VID AMD_SB_VID // dev 20 Func 0
408#define V_SB_SMBUS_DID 0x4385
409#define V_SB_IDE_VID AMD_SB_VID // dev 20 Func 1
410#define V_SB_IDE_DID 0x439C
411#define V_SB_AZALIA_VID AMD_SB_VID // dev 20 Func 2
412#define V_SB_AZALIA_DID 0x4383
413#define V_SB_LPC_VID AMD_SB_VID // dev 20 Func 3
414#define V_SB_LPC_DID 0x439D
415#define V_SB_PCIB_VID AMD_SB_VID // dev 20 Func 4
416#define V_SB_PCIB_DID 0x4384
417#define V_SB_USB_OHCIF_VID AMD_SB_VID // dev 20 Func 5
418#define V_SB_USB_OHCIF_DID 0x4399
419#define V_SB_NIC_VID 0x14E4 // dev 20 Func 6
420#define V_SB_NIC_DID 0x1699
421
422//Misc
423#define ACPI_SMI_CMD_PORT 0xB0
424#define ACPI_SMI_DATA_PORT 0xB1
425#define R_SB_ACPI_PM1_STATUS 0x00
426#define R_SB_ACPI_PM1_ENABLE 0x02
427#define R_SB_ACPI_PM_CONTROL 0x04
428#define R_SB_ACPI_EVENT_STATUS 0x20
429#define R_SB_ACPI_EVENT_ENABLE 0x24
430#define R_SB_PM_ACPI_PMA_CNT_BLK_LO 0x2C
431
432#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
433#define SB_SATA1_BUS 0
434#define SB_SATA1_DEV 17
435#define SB_SATA1_FUNC 0
436
437#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
438#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
439#define SB_OHCI1_BUS 0
440#define SB_OHCI1_DEV 18
441#define SB_OHCI1_FUNC 0
442#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
443#define SB_OHCI2_BUS 0
444#define SB_OHCI2_DEV 19
445#define SB_OHCI2_FUNC 0
446#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
447#define SB_OHCI3_BUS 0
448#define SB_OHCI3_DEV 22
449#define SB_OHCI3_FUNC 0
450#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
451#define SB_EHCI1_BUS 0
452#define SB_EHCI1_DEV 18
453#define SB_EHCI1_FUNC 2
454#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
455#define SB_EHCI2_BUS 0
456#define SB_EHCI2_DEV 19
457#define SB_EHCI2_FUNC 2
458#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
459#define SB_EHCI3_BUS 0
460#define SB_EHCI3_DEV 22
461#define SB_EHCI3_FUNC 2
462
463#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
464#define SB_ISA_BUS 0
465#define SB_ISA_DEV 20
466#define SB_ISA_FUNC 0
467#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
468#define SB_IDE_BUS 0
469#define SB_IDE_DEV 20
470#define SB_IDE_FUNC 1
471#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
472#define SB_AZALIA_BUS 0
473#define SB_AZALIA_DEV 20
474#define SB_AZALIA_FUNC 2
475#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
476#define SB_LPC_BUS 0
477#define SB_LPC_DEV 20
478#define SB_LPC_FUNC 3
479#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
480#define SB_PCI_BUS 0
481#define SB_PCI_DEV 20
482#define SB_PCI_FUNC 4
483#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
484#define SB_OHCI4_BUS 0
485#define SB_OHCI4_DEV 20
486#define SB_OHCI4_FUNC 5
487//Gigabyte Ethernet Controller
488#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
489#define SB_GBEC_BUS 0
490#define SB_GBEC_DEV 20
491#define SB_GBEC_FUNC 6
492
493#define SB_GPP_BUS 0
494#define SB_GPP_DEV 21
495#define SB_GPP_FUNC 0
496#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
497#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
498#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
499#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
500
501#define ACPI_MMIO_BASE 0xFED80000
502#define SB_CFG_BASE 0x000 // DWORD
503#define GPIO_BASE 0x100 // BYTE
504#define SMI_BASE 0x200 // DWORD
505#define PMIO_BASE 0x300 // DWORD
506#define PMIO2_BASE 0x400 // BYTE
507#define BIOS_RAM_BASE 0x500 // BYTE
508#define CMOS_RAM_BASE 0x600 // BYTE
509#define CMOS_BASE 0x700 // BYTE
510#define ASF_BASE 0x900 // DWORD
511#define SMBUS_BASE 0xA00 // DWORD
512#define WATCHDOG_BASE 0xB00 // ??
513#define HPET_BASE 0xC00 // DWORD
514#define IOMUX_BASE 0xD00 // BYTE
515#define MISC_BASE 0xE00
516
517#define GPP_EFUSE_LOCATION 0x14 // bit 160
518#define GPP_GEN2_EFUSE_BIT BIT0
519
520// RegSpace field (AB_INDEX[31:29]
521#define AXINDC 0 // AXINDC
522#define AXINDP 2 // AXINDP
523#define ABCFG 6 // ABCFG
524#define AXCFG 4 // AXCFG
525#define RCINDXC 1 // PCIEIND
526#define RCINDXP 3 // PCIEIND_P
527
528#define SBTEMP_BUS 8
529#define GPP_DEV_NUM 21 //?? Code style different
530#define MAX_GPP_PORTS 4
531#ifndef TRUE
532 #define TRUE 1
533#endif
534#ifndef FALSE
535 #define FALSE 0
536#endif
537//
538// ABCFG Registers
539//
540#define SB_ABCFG_REG00 0x00 // VENDOR ID
541#define SB_ABCFG_REG08 0x08 // REVISION ID
542#define SB_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
543#define SB_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
544#define SB_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
545#define SB_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
546#define SB_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
547#define SB_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
548#define SB_ABCFG_REG50 0x50 // MISCCTL_50
549#define SB_ABCFG_REG54 0x54 // MISCCTL_54
550#define SB_ABCFG_REG58 0x58 // BL RAB CONTROL
551
552#define SB_ABCFG_REG60 0x60 // LINKWIDTH_CTL
553#define SB_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
554#define SB_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
555#define SB_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
556#define SB_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
557#define SB_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
558#define SB_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
559
560#define SB_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
561#define SB_ABCFG_REG88 0x88 //
562#define SB_ABCFG_REG90 0x90 // BIF CONTROL 0
563#define SB_ABCFG_REG94 0x94 // MSI CONTROL
564#define SB_ABCFG_REG98 0x98 // BIF CONTROL 1
565#define SB_ABCFG_REG9C 0x9C // MISCCTL_9C
566#define SB_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
567#define SB_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
568#define SB_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
569#define SB_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
570#define SB_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
571#define SB_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
572#define SB_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
573#define SB_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
574#define SB_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
575#define SB_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
576#define SB_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
577#define SB_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
578#define SB_ABCFG_REGFC 0xFC // SB_TRAP_CONTROL
579#define SB_ABCFG_REG100 0x100 // SB_TRAP0_ADDRL
580#define SB_ABCFG_REG104 0x104 // SB_TRAP0_ADDRH
581#define SB_ABCFG_REG108 0x108 // SB_TRAP0_CMD
582#define SB_ABCFG_REG10C 0x10C // SB_TRAP1_DATA
583#define SB_ABCFG_REG110 0x110 // SB_TRAP1_ADDRL
584#define SB_ABCFG_REG114 0x114 // SB_TRAP1_ADDRH
585#define SB_ABCFG_REG118 0x118 // SB_TRAP1_CMD
586#define SB_ABCFG_REG11C 0x11C // SB_TRAP1_DATA
587#define SB_ABCFG_REG120 0x120 // SB_TRAP2_ADDRL
588#define SB_ABCFG_REG124 0x124 // SB_TRAP2_ADDRH
589#define SB_ABCFG_REG128 0x128 // SB_TRAP2_CMD
590#define SB_ABCFG_REG12C 0x12C // SB_TRAP2_DATA
591#define SB_ABCFG_REG130 0x130 // SB_TRAP3_ADDRL
592#define SB_ABCFG_REG134 0x134 // SB_TRAP3_ADDRH
593#define SB_ABCFG_REG138 0x138 // SB_TRAP3_CMD
594#define SB_ABCFG_REG13C 0x13C // SB_TRAP3_DATA
595#define SB_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
596#define SB_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
597#define SB_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
598#define SB_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
599#define SB_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
600#define SB_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
601#define SB_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
602#define SB_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
603#define SB_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
604#define SB_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
605#define SB_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
606#define SB_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
607#define SB_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
608#define SB_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
609#define SB_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
610#define SB_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
611#define SB_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
612#define SB_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
613#define SB_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
614#define SB_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
615#define SB_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
616#define SB_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
617#define SB_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
618#define SB_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
619#define SB_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
620#define SB_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
621#define SB_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
622#define SB_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
623#define SB_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
624#define SB_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
625#define SB_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
626#define SB_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
627#define SB_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
628#define SB_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
629#define SB_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
630#define SB_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
631#define SB_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
632#define SB_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
633#define SB_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
634#define SB_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
635#define SB_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
636#define SB_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
637#define SB_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
638#define SB_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
639#define SB_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
640#define SB_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
641#define SB_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
642#define SB_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
643#define SB_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
644#define SB_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
645#define SB_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
646#define SB_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
647#define SB_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
648#define SB_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO
649#define SB_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO
650#define SB_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL
651#define SB_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI
652#define SB_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI
653#define SB_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL
654#define SB_ABCFG_REG10050 0x10050 // MISCCTL_10050
655#define SB_ABCFG_REG10054 0x10054 // AL_ARB_CTL
656#define SB_ABCFG_REG10056 0x10056 // AL_CLK_CTL
657#define SB_ABCFG_REG10058 0x10058 // AL RAB CONTROL
658#define SB_ABCFG_REG1005C 0x1005C // AL MLT CONTROL
659#define SB_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE
660#define SB_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL
661#define SB_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT
662#define SB_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL
663#define SB_ABCFG_REG10070 0x10070 // MISCCTL_10070
664#define SB_ABCFG_REG10080 0x10080 // CLKMUXSTATUS
665#define SB_ABCFG_REG10090 0x10090 // BIF CONTROL 0
666#define SB_ABCFG_REG1009C 0x1009C // MISCCTL_1009C
667
668//
669// RCINDX_P Registers
670//
671#define SB_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
672#define SB_RCINDXP_REG10 0x10 | RCINDXP << 29 //
673#define SB_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
674#define SB_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
675#define SB_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
676#define SB_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
677#define SB_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
678#define SB_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
679#define SB_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
680#define SB_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
681#define SB_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
682
683//
684// RCINDX_C Registers
685//
686#define SB_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
687#define SB_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
688#define SB_RCINDXC_REGC1 0xC1 | RCINDXC << 29 //
689
690//
691// AXINDC Registers
692//
693#define SB_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
694#define SB_AX_INDXC_REG10 0x10
695#define SB_AX_INDXC_REG30 0x30
696#define SB_AX_DATAC_REG34 0x34
697#define SB_AX_INDXP_REG38 0x38
698#define SB_AX_DATAP_REG3C 0x3C
699#define SB_AX_INDXC_REG40 0x40 | AXINDC << 29
700#define SB_AX_INDXC_REGA4 0xA4 | AXINDC << 29
701
702#define SB_AX_INDXP_REGA0 0xA0 | AXINDP << 29
703#define SB_AX_INDXP_REGA4 0xA4 | AXINDP << 29
704#define SB_AX_INDXP_REGB1 0xB1 | AXINDP << 29
705
706#define SB_AX_CFG_REG88 0x88 | AXCFG << 29
707
708#define AX_INDXC 0
709#define AX_INDXP 1
710#define SB_AB_REG04 0x04
711#define SB_AB_REG40 0x40
712
713#define RC_INDXC_REG40 0x40 | RCINDXC << 29
714#define RC_INDXC_REG65 0x65 | RCINDXC << 29
715
716//
717// SATA Device 0x4390 (IDE)
718// 0x4391 (AHCI)
719// 0x4392 (AHCI/RAID Promise with RAID driver)
720// 0x4393 (RAID5)
721// 0x4394/0x4395 (SATA HyperFlash OneNand support/SATA HyperFlash-PCIe support)
722// Device 17 (0x11) Func 0
723//
724//Sata Controller Mode
725#define NATIVE_IDE_MODE 0
726#define RAID_MODE 1
727#define AHCI_MODE 2
728#define LEGACY_IDE_MODE 3
729#define IDE_TO_AHCI_MODE 4
730#define AHCI_MODE_4394 5
731#define IDE_TO_AHCI_MODE_4394 6
732
733//Sata Port Configuration
734#define SIX_PORTS 0
735#define FOUR_PORTS 1
736
737#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
738#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
739#define SATA_EFUSE_BIT 0x20 //
740#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits
741#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits
742#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits
743#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits
744#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
745#define SB_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
746#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
747#define SB_SATA_REG0E 0x00E // Header Type - R - 8 bits
748#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits
749#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
750#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
751#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
752#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
753#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
754#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
755#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
756#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
757#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
758#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
759#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
760#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
761#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits
762#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits
763#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits
764#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
765#define SB_SATA_REG48 0x048
766#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits
767#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits
768#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits
769#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits
770#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
771#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
772#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
773#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
774#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
775#define SB_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
776#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
777#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
778#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
779#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
780#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
781#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
782#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
783#define SB_SATA_REG86 0x086 // PY Global Control
784#define SB_SATA_REG87 0x087
785#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
786#define SB_SATA_REG8A 0x08A
787#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
788#define SB_SATA_REG8E 0x08E
789#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
790#define SB_SATA_REG92 0x092
791#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
792#define SB_SATA_REG96 0x096
793#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
794#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
795#define SB_SATA_REGA0 0x0A0 //
796#define SB_SATA_REGA4 0x0A4 //
797#define SB_SATA_REGA5 0x0A5 //;
798#define SB_SATA_REGA8 0x0A8 //
799#define SB_SATA_REGAD 0x0AD //;
800#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
801#define SB_SATA_REGB5 0x0B5 //;
802#define SB_SATA_REGBD 0x0BD //;
803#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
804#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
805
806#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
807#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
808#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
809#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
810#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
811#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
812#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
813#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
814#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
815#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
816#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
817#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
818#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
819#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
820#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
821#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
822#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
823#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
824#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
825#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
826#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
827#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
828#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
829#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
830#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
831#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
832#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
833#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
834#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
835#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
836#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
837#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
838#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
839#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
840#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
841#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
842#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
843#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
844#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
845#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
846#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
847#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
848#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
849#define SB_SATA_BAR5_REGFC 0x0FC
850#define SB_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
851#define SB_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
852#define SB_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
853#define SB_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
854#define SB_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
855#define SB_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
856#define SB_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
857#define SB_SATA_BAR5_REG120 0x0120 //
858#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
859#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
860#define SB_SATA_BAR5_REG130 0x0130
861#define SB_SATA_BAR5_REG1B0 0x01B0
862#define SB_SATA_BAR5_REG230 0x0230
863#define SB_SATA_BAR5_REG2B0 0x02B0
864#define SB_SATA_BAR5_REG330 0x0330
865#define SB_SATA_BAR5_REG3B0 0x03B0
866
867//
868// FC Device 0x439B
869// Device 17 (0x11) Func 1
870//
871#define SB_FC_REG00 0x00 // Device/Vendor ID - R
872#define SB_FC_REG04 0x04 // Command - RW
873#define SB_FC_REG10 0x10 // BAR
874
875#define SB_FC_MMIO_REG70 0x070
876#define SB_FC_MMIO_REG200 0x200
877
878//
879// USB OHCI Device 0x4397
880// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
881// Device 20 (0x14) Func 5 (FL)
882//
883#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002)
884#define SB_OHCI_REG04 0x04 // Command - RW
885#define SB_OHCI_REG06 0x06 // Status - R
886#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R
887#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW
888#define SB_OHCI_REG10 0x10 // Bar_OCI - RW
889#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
890#define SB_OHCI_REG34 0x34 // Capability Pointer - R
891#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW
892#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW
893#define SB_OHCI_REG40 0x40 // Config Timers - RW
894#define SB_OHCI_REG42 0x42 // Port Disable Control - RW (800)
895#define SB_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
896#define SB_OHCI_REG48 0x48 // Port Force Reset - RW (800)
897#define SB_OHCI_REG4C 0x4C // MSI - RW (800)
898#define SB_OHCI_REG50 0x50 // Misc Control - RW
899#define SB_OHCI_REG51 0x51
900#define SB_OHCI_REG52 0x52
901#define SB_OHCI_REG58 0x58 // Over Current Control - RW
902#define SB_OHCI_REG5C 0x5C // Over Current Control - RW (800)??
903#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R (800)??
904#define SB_OHCI_REG68 0x68 // Over Current PME Enable - RW
905#define SB_OHCI_REG74 0x74 // Target Timeout Control - RW (800)
906#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW
907#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW
908#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW
909#define SB_OHCI_REGE4 0x0E4 // HT MSI Support
910#define SB_OHCI_REGF0 0x0F0 // Function Level Reset Capability
911#define SB_OHCI_REGF4 0x0F4 // Function Level Reset Control
912
913#define SB_OHCI_BAR_REG00 0x00 // cRevision - R
914#define SB_OHCI_BAR_REG04 0x04 // cControl
915#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus
916#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
917#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable
918#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable
919#define SB_OHCI_BAR_REG18 0x18 // HcCCA
920#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
921#define SB_OHCI_BAR_REG20 0x20 // HcControleadED
922#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
923#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED
924#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
925#define SB_OHCI_BAR_REG30 0x30 // HcDoneead
926#define SB_OHCI_BAR_REG34 0x34 // cFmInterval
927#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining
928#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber
929#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart
930#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold
931#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA
932#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
933#define SB_OHCI_BAR_REG50 0x50 // HcRStatus
934#define SB_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
935#define SB_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
936#define SB_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
937
938//
939// USB EHCI Device 0x4396
940// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
941//
942#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
943#define SB_EHCI_REG04 0x04 // Command - RW
944#define SB_EHCI_REG06 0x06 // Status - R
945#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R
946#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW
947#define SB_EHCI_REG10 0x10 // BAR - RW
948#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
949#define SB_EHCI_REG34 0x34 // Capability Pointer - R
950#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW
951#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW ??
952#define SB_EHCI_REG40 0x40 // Config Timers - RW ??
953#define SB_EHCI_REG4C 0x4C // MSI - RW
954#define SB_EHCI_REG50 0x50 // EHCI Misc Control - RW
955#define SB_EHCI_REG54 0x54 // EHCI Misc Control - RW
956#define SB_EHCI_REG60 0x60 // SBRN - R
957#define SB_EHCI_REG61 0x61 // FLADJ - RW
958#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW
959#define SB_EHCI_REGC0 0x0C0 // PME control - RW (800)
960#define SB_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
961#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW
962#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW
963#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW
964#define SB_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
965#define SB_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
966#define SB_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
967
968#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R
969#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R
970#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R
971#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R
972#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
973
974#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
975#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
976#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
977#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
978#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
979#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
980#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
981#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
982#define SB_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
983#define SB_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
984#define SB_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
985#define SB_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
986#define SB_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
987#define SB_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
988#define SB_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
989#define SB_EHCI_BAR_REGB8 0x0B8 // Loopback Test
990#define SB_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
991#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
992#define SB_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
993#define SB_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
994#define SB_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
995#define SB_EHCI_BAR_REG100 0x100 // USB debug port
996
997//
998// SB800 SB CFG device 0x4385
999// Device 20 (0x14) Func 0
1000//
1001#define SB_CFG_REG00 0x000 // VendorID - R
1002#define SB_CFG_REG02 0x002 // DeviceID - R
1003#define SB_CFG_REG04 0x004 // Command- RW
1004#define SB_CFG_REG05 0x005 // Command- RW
1005#define SB_CFG_REG06 0x006 // STATUS- RW
1006#define SB_CFG_REG08 0x008 // Revision ID/Class Code- R
1007#define SB_CFG_REG0A 0x00A //
1008#define SB_CFG_REG0B 0x00B //
1009#define SB_CFG_REG0C 0x00C // Cache Line Size- R
1010#define SB_CFG_REG0D 0x00D // Latency Timer- R
1011#define SB_CFG_REG0E 0x00E // Header Type- R
1012#define SB_CFG_REG0F 0x00F // BIST- R
1013#define SB_CFG_REG10 0x010 // Base Address 0- R
1014#define SB_CFG_REG11 0x011 //;
1015#define SB_CFG_REG12 0x012 //;
1016#define SB_CFG_REG13 0x013 //;
1017#define SB_CFG_REG14 0x014 // Base Address 1- R
1018#define SB_CFG_REG18 0x018 // Base Address 2- R
1019#define SB_CFG_REG1C 0x01C // Base Address 3- R
1020#define SB_CFG_REG20 0x020 // Base Address 4- R
1021#define SB_CFG_REG24 0x024 // Base Address 5- R
1022#define SB_CFG_REG28 0x028 // Cardbus CIS Pointer- R
1023#define SB_CFG_REG2C 0x02C // Subsystem Vendor ID- W
1024#define SB_CFG_REG2E 0x02E // Subsystem ID- W
1025#define SB_CFG_REG30 0x030 // Expansion ROM Base Address - R
1026#define SB_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
1027#define SB_CFG_REG3C 0x03C // Interrupt Line - R
1028#define SB_CFG_REG3D 0x03D // Interrupt Pin - R
1029#define SB_CFG_REG3E 0x03E // Min_Gnt - R
1030#define SB_CFG_REG3F 0x03F // Max_Lat - R
1031#define SB_CFG_REG90 0x090 // Smbus Base Address - R
1032#define SB_CFG_REG9C 0x09C // SBResourceMMIO_BASE
1033
1034//
1035// SB800 SATA IDE device 0x439C
1036// Device 20 (0x14) Func 1
1037//
1038
1039#define SB_IDE_REG00 0x00 // Vendor ID
1040#define SB_IDE_REG02 0x02 // Device ID
1041#define SB_IDE_REG04 0x04 // Command
1042#define SB_IDE_REG06 0x06 // Status
1043#define SB_IDE_REG08 0x08 // Revision ID/Class Code
1044#define SB_IDE_REG09 0x09 // Class Code
1045#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
1046#define SB_IDE_REG34 0x34
1047#define SB_IDE_REG40 0x40 // Configuration - RW - 32 bits
1048#define SB_IDE_REG62 0x62 // IDE Internal Control
1049#define SB_IDE_REG63 0x63 // IDE Internal Control
1050//
1051// SB800 AZALIA device 0x4383
1052// Device 20 (0x14) Func 2
1053//
1054#define ATI_AZALIA_ExtBlk_Addr 0x0F8
1055#define ATI_AZALIA_ExtBlk_DATA 0x0FC
1056
1057#define SB_AZ_REG00 0x00 // Vendor ID - R
1058#define SB_AZ_REG02 0x02 // Device ID - R/W
1059#define SB_AZ_REG04 0x04 // PCI Command
1060#define SB_AZ_REG06 0x06 // PCI Status - R/W
1061#define SB_AZ_REG08 0x08 // Revision ID
1062#define SB_AZ_REG09 0x09 // Programming Interface
1063#define SB_AZ_REG0A 0x0A // Sub Class Code
1064#define SB_AZ_REG0B 0x0B // Base Class Code
1065#define SB_AZ_REG0C 0x0C // Cache Line Size - R/W
1066#define SB_AZ_REG0D 0x0D // Latency Timer
1067#define SB_AZ_REG0E 0x0E // Header Type
1068#define SB_AZ_REG0F 0x0F // BIST
1069#define SB_AZ_REG10 0x10 // Lower Base Address Register
1070#define SB_AZ_REG14 0x14 // Upper Base Address Register
1071#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID
1072#define SB_AZ_REG2D 0x2D // Subsystem ID
1073#define SB_AZ_REG34 0x34 // Capabilities Pointer
1074#define SB_AZ_REG3C 0x3C // Interrupt Line
1075#define SB_AZ_REG3D 0x3D // Interrupt Pin
1076#define SB_AZ_REG3E 0x3E // Minimum Grant
1077#define SB_AZ_REG3F 0x3F // Maximum Latency
1078#define SB_AZ_REG40 0x40 // Misc Control 1
1079#define SB_AZ_REG42 0x42 // Misc Control 2 Register
1080#define SB_AZ_REG43 0x43 // Misc Control 3 Register
1081#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register
1082#define SB_AZ_REG46 0x46 // Debug Control Register
1083#define SB_AZ_REG4C 0x4C
1084#define SB_AZ_REG50 0x50 // Power Management Capability ID
1085#define SB_AZ_REG52 0x52 // Power Management Capabilities
1086#define SB_AZ_REG54 0x54 // Power Management Control/Status
1087#define SB_AZ_REG60 0x60 // MSI Capability ID
1088#define SB_AZ_REG62 0x62 // MSI Message Control
1089#define SB_AZ_REG64 0x64 // MSI Message Lower Address
1090#define SB_AZ_REG68 0x68 // MSI Message Upper Address
1091#define SB_AZ_REG6C 0x6C // MSI Message Data
1092
1093#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R
1094#define SB_AZ_BAR_REG02 0x02 // Minor Version - R
1095#define SB_AZ_BAR_REG03 0x03 // Major Version - R
1096#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R
1097#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R
1098#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W
1099#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
1100#define SB_AZ_BAR_REG0E 0x0E // State Change Status - R/W
1101#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W
1102#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
1103#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
1104#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
1105#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
1106#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
1107#define SB_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
1108#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
1109#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
1110#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
1111#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
1112#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W
1113#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W
1114#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W
1115#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
1116#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
1117#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
1118#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
1119#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
1120#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
1121#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
1122#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
1123#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
1124#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
1125#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
1126#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
1127#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
1128
1129//
1130// SB800 LPC Device 0x439D
1131// Device 20 (0x14) Func 3
1132//
1133#define SB_LPC_REG00 0x00 // VID- R
1134#define SB_LPC_REG02 0x02 // DID- R
1135#define SB_LPC_REG04 0x04 // CMD- RW
1136#define SB_LPC_REG06 0x06 // STATUS- RW
1137#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R
1138#define SB_LPC_REG0C 0x0C // Cache Line Size - R
1139#define SB_LPC_REG0D 0x0D // Latency Timer - R
1140#define SB_LPC_REG0E 0x0E // Header Type - R
1141#define SB_LPC_REG0F 0x0F // BIST- R
1142#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW*
1143#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
1144#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro
1145#define SB_LPC_REG40 0x40 // PCI Control - RW
1146#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
1147#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
1148#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
1149#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
1150#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
1151#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
1152#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
1153#define SB_LPC_REG4C 0x4C // Memory Range Register - RW
1154#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW
1155#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW
1156#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW
1157#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW
1158#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
1159#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
1160#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
1161#define SB_LPC_REG65 0x65
1162#define SB_LPC_REG66 0x66
1163#define SB_LPC_REG67 0x67
1164#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
1165#define SB_LPC_REG69 0x69
1166#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
1167#define SB_LPC_REG6B 0x6B
1168#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
1169#define SB_LPC_REG6D 0x6D
1170#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
1171#define SB_LPC_REG6F 0x6F
1172#define SB_LPC_REG70 0x70 // Firmware ub Select - RW*
1173#define SB_LPC_REG71 0x71
1174#define SB_LPC_REG72 0x72
1175#define SB_LPC_REG73 0x73
1176#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
1177#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
1178#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
1179#define SB_LPC_REG9C 0x9C
1180#define SB_LPC_REG80 0x80 // MSI Capability Register- R
1181#define SB_LPC_REGA0 0x0A0 // SPI base address
1182#define SB_LPC_REGA1 0x0A1 // SPI base address
1183#define SB_LPC_REGA2 0x0A2 // SPI base address
1184#define SB_LPC_REGA3 0x0A3 // SPI base address
1185#define SB_LPC_REGA4 0x0A4
1186#define SB_LPC_REGBA 0x0BA // EcControl
1187#define SB_LPC_REGBB 0x0BB // HostControl
1188
1189//
1190// SB800 PCIB 0x4384
1191// Device 20 (0x14) Func 4
1192//
1193#define SB_PCIB_REG04 0x04 // Command
1194#define SB_PCIB_REG0D 0x0D // Primary Master Latency Timer
1195#define SB_PCIB_REG1B 0x1B // Secondary Latency Timer
1196#define SB_PCIB_REG1C 0x1C // IO Base
1197#define SB_PCIB_REG1D 0x1D // IO Limit
1198#define SB_PCIB_REG40 0x40 // CPCTRL
1199#define SB_PCIB_REG42 0x42 // CLKCTRL
1200#define SB_PCIB_REG48 0x48 //
1201#define SB_PCIB_REG4A 0x4A // PCICLK Enable Bits
1202#define SB_PCIB_REG4B 0x4B // Misc Control
1203#define SB_PCIB_REG4C 0x4C // AutoClockRun Control
1204#define SB_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
1205#define SB_PCIB_REG65 0x65 // Misc Control
1206#define SB_PCIB_REG66 0x66 // Misc Control
1207//
1208// SB800 NIC 0x4384
1209// Device 20 (0x14) Func 6 (Func5 OHCI FL device)
1210//
1211#define SB_GEC_REG04 0x04 // Command
1212#define SB_GEC_REG10 0x10 // GEC BAR
1213
1214//
1215// SB800 SB MMIO Base (SMI)
1216// offset : 0x200
1217//
1218#define SB_SMI_REG00 0x00 // EventStatus
1219#define SB_SMI_REG04 0x04 // EventEnable
1220#define SB_SMI_REG08 0x08 // SciTrig
1221#define SB_SMI_REG0C 0x0C // SciLevl
1222#define SB_SMI_REG10 0x10 // SmiSciStatus
1223#define SB_SMI_REG14 0x14 // SmiSciEn
1224#define SB_SMI_REG18 0x18 // ForceSciEn
1225#define SB_SMI_REG1C 0x1C // SciRwData
1226#define SB_SMI_REG20 0x20 // SciS0En
1227#define SB_SMI_Gevent0 0x40 // SciMap0
1228#define SB_SMI_Gevent1 0x41 // SciMap1
1229#define SB_SMI_Gevent2 0x42 // SciMap2
1230#define SB_SMI_Gevent3 0x43 // SciMap3
1231#define SB_SMI_Gevent4 0x44 // SciMap4
1232#define SB_SMI_Gevent5 0x45 // SciMap5
1233#define SB_SMI_Gevent6 0x46 // SciMap6
1234#define SB_SMI_Gevent7 0x47 // SciMap7
1235#define SB_SMI_Gevent8 0x48 // SciMap8
1236#define SB_SMI_Gevent9 0x49 // SciMap9
1237#define SB_SMI_Gevent10 0x4A // SciMap10
1238#define SB_SMI_Gevent11 0x4B // SciMap11
1239#define SB_SMI_Gevent12 0x4C // SciMap12
1240#define SB_SMI_Gevent13 0x4D // SciMap13
1241#define SB_SMI_Gevent14 0x4E // SciMap14
1242#define SB_SMI_Gevent15 0x4F // SciMap15
1243#define SB_SMI_Gevent16 0x50 // SciMap16
1244#define SB_SMI_Gevent17 0x51 // SciMap17
1245#define SB_SMI_Gevent18 0x52 // SciMap18
1246#define SB_SMI_Gevent19 0x53 // SciMap19
1247#define SB_SMI_Gevent20 0x54 // SciMap20
1248#define SB_SMI_Gevent21 0x55 // SciMap21
1249#define SB_SMI_Gevent22 0x56 // SciMap22
1250#define SB_SMI_Gevent23 0x57 // SciMap23
1251#define SB_SMI_Usbwakup0 0x58 // SciMap24
1252#define SB_SMI_Usbwakup1 0x59 // SciMap25
1253#define SB_SMI_Usbwakup2 0x5A // SciMap26
1254#define SB_SMI_Usbwakup3 0x5B // SciMap27
1255#define SB_SMI_SBGppPme0 0x5C // SciMap28
1256#define SB_SMI_SBGppPme1 0x5D // SciMap29
1257#define SB_SMI_SBGppPme2 0x5E // SciMap30
1258#define SB_SMI_SBGppPme3 0x5F // SciMap31
1259#define SB_SMI_SBGppHp0 0x60 // SciMap32
1260#define SB_SMI_SBGppHp1 0x61 // SciMap33
1261#define SB_SMI_SBGppHp2 0x62 // SciMap34
1262#define SB_SMI_SBGppHp3 0x63 // SciMap35
1263#define SB_SMI_AzaliaPme 0x64 // SciMap36
1264#define SB_SMI_SataGevent0 0x65 // SciMap37
1265#define SB_SMI_SataGevent1 0x66 // SciMap38
1266#define SB_SMI_GecPme 0x67 // SciMap39
1267#define SB_SMI_IMCGevent0 0x68 // SciMap40
1268#define SB_SMI_IMCGevent1 0x69 // SciMap41
1269#define SB_SMI_CIRPme 0x6A // SciMap42
1270#define SB_SMI_WakePinGevent 0x6B // SciMap43
1271#define SB_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
1272#define SB_SMI_ASFMasterIntr 0x6D // SciMap45
1273#define SB_SMI_ASFSlaveIntr 0x6E // SciMap46
1274#define SB_SMI_SMBUS0 0x6F // SciMap47
1275#define SB_SMI_TWARN 0x70 // SciMap48
1276#define SB_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
1277
1278// Empty from 0x72-0x7F
1279//#Define SB_SMI_REG7C 0x7F // SciMap63 ***
1280
1281#define SB_SMI_REG80 0x80 // SmiStatus0
1282#define SB_SMI_REG84 0x84 // SmiStatus1
1283#define SB_SMI_REG88 0x88 // SmiStatus2
1284#define SB_SMI_REG8C 0x8C // SmiStatus3
1285#define SB_SMI_REG90 0x90 // SmiStatus4
1286#define SB_SMI_REG94 0x94 // SmiPointer
1287#define SB_SMI_REG96 0x96 // SmiTimer
1288#define SB_SMI_REG98 0x98 // SmiTrig
1289#define SB_SMI_REG9C 0x9C // SmiTrig
1290#define SB_SMI_REGA0 0xA0
1291#define SB_SMI_REGA1 0xA1
1292#define SB_SMI_REGA2 0xA2
1293#define SB_SMI_REGA3 0xA3
1294#define SB_SMI_REGA4 0xA4
1295#define SB_SMI_REGA5 0xA5
1296#define SB_SMI_REGA6 0xA6
1297#define SB_SMI_REGA7 0xA7
1298#define SB_SMI_REGA8 0xA8
1299#define SB_SMI_REGA9 0xA9
1300#define SB_SMI_REGAA 0xAA
1301#define SB_SMI_REGAB 0xAB
1302#define SB_SMI_REGAC 0xAC
1303#define SB_SMI_REGAD 0xAD
1304#define SB_SMI_REGAE 0xAE
1305#define SB_SMI_REGAF 0xAF
1306#define SB_SMI_REGB0 0xB0
1307#define SB_SMI_REGB1 0xB1
1308#define SB_SMI_REGB2 0xB2
1309#define SB_SMI_REGB3 0xB3
1310#define SB_SMI_REGB4 0xB4
1311#define SB_SMI_REGB5 0xB5
1312#define SB_SMI_REGB6 0xB6
1313#define SB_SMI_REGB7 0xB7
1314#define SB_SMI_REGB8 0xB8
1315#define SB_SMI_REGB9 0xB9
1316#define SB_SMI_REGBA 0xBA
1317#define SB_SMI_REGBB 0xBB
1318#define SB_SMI_REGBC 0xBC
1319#define SB_SMI_REGBD 0xBD
1320#define SB_SMI_REGBE 0xBE
1321#define SB_SMI_REGBF 0xBF
1322#define SB_SMI_REGC0 0xC0
1323#define SB_SMI_REGC1 0xC1
1324#define SB_SMI_REGC2 0xC2
1325#define SB_SMI_REGC3 0xC3
1326#define SB_SMI_REGC4 0xC4
1327#define SB_SMI_REGC5 0xC5
1328#define SB_SMI_REGC6 0xC6
1329#define SB_SMI_REGC7 0xC7
1330#define SB_SMI_REGC8 0xC8
1331#define SB_SMI_REGCA 0xCA // IoTrapping1
1332#define SB_SMI_REGCC 0xCC // IoTrapping2
1333#define SB_SMI_REGCE 0xCE // IoTrapping3
1334#define SB_SMI_REGD0 0xD0 // MemTrapping0
1335#define SB_SMI_REGD4 0xD4 // MemRdOvrData0
1336#define SB_SMI_REGD8 0xD8 // MemTrapping1
1337#define SB_SMI_REGDC 0xDC // MemRdOvrData1
1338#define SB_SMI_REGE0 0xE0 // MemTrapping2
1339#define SB_SMI_REGE4 0xE4 // MemRdOvrData2
1340#define SB_SMI_REGE8 0xE8 // MemTrapping3
1341#define SB_SMI_REGEC 0xEC // MemRdOvrData3
1342#define SB_SMI_REGF0 0xF0 // CfgTrapping0
1343#define SB_SMI_REGF4 0xF4 // CfgTrapping1
1344#define SB_SMI_REGF8 0xF8 // CfgTrapping2
1345#define SB_SMI_REGFC 0xFC // CfgTrapping3
1346
1347//
1348// SB800 SB MMIO Base (PMIO)
1349// offset : 0x300
1350//
1351#define SB_PMIOA_REG00 0x00 // ISA Decode
1352#define SB_PMIOA_REG04 0x04 // ISA Control
1353#define SB_PMIOA_REG08 0x08 // PCI Control
1354#define SB_PMIOA_REG0C 0x0C // StpClkSmaf
1355#define SB_PMIOA_REG10 0x10 // RetryDetect
1356#define SB_PMIOA_REG14 0x14 // StuckDetect
1357#define SB_PMIOA_REG20 0x20 // BiosRamEn
1358#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
1359#define SB_PMIOA_REG28 0x28 // AsfEn
1360#define SB_PMIOA_REG2C 0x2C // Smbus0En
1361#define SB_PMIOA_REG34 0x34 // IoApicEn
1362#define SB_PMIOA_REG3C 0x3C // SmartVoltEn
1363#define SB_PMIOA_REG40 0x40 // SmartVolt2En
1364#define SB_PMIOA_REG44 0x44 // BootTimerEn
1365#define SB_PMIOA_REG48 0x48 // WatchDogTimerEn
1366#define SB_PMIOA_REG4C 0x4C // WatchDogTimerConfig
1367#define SB_PMIOA_REG50 0x50 // HPETEn
1368#define SB_PMIOA_REG54 0x54 // SerialIrqConfig
1369#define SB_PMIOA_REG56 0x56 // RtcControl
1370#define SB_PMIOA_REG58 0x58 // VRT_T1
1371#define SB_PMIOA_REG59 0x59 // VRT_T2
1372#define SB_PMIOA_REG5A 0x5A // IntruderControl
1373#define SB_PMIOA_REG5B 0x5B // RtcShadow
1374#define SB_PMIOA_REG5C 0x5C
1375#define SB_PMIOA_REG5D 0x5D
1376#define SB_PMIOA_REG5E 0x5E // RtcExtIndex
1377#define SB_PMIOA_REG5F 0x5F // RtcExtData
1378#define SB_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
1379#define SB_PMIOA_REG62 0x62 // AcpiPm1CntBlk
1380#define SB_PMIOA_REG64 0x64 // AcpiPmTmrBlk
1381#define SB_PMIOA_REG66 0x66 // P_CNTBlk
1382#define SB_PMIOA_REG68 0x68 // AcpiGpe0Blk
1383#define SB_PMIOA_REG6A 0x6A // AcpiSmiCmd
1384#define SB_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
1385#define SB_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
1386#define SB_PMIOA_REG74 0x74 // AcpiConfig
1387#define SB_PMIOA_REG78 0x78 // WakeIoAddr
1388#define SB_PMIOA_REG7A 0x7A // HaltCountEn
1389#define SB_PMIOA_REG7C 0x7C // C1eWrPortAdr
1390#define SB_PMIOA_REG7E 0x7E // CStateEn
1391#define SB_PMIOA_REG80 0x80 // BreakEvent
1392#define SB_PMIOA_REG84 0x84 // AutoArbEn
1393#define SB_PMIOA_REG88 0x88 // CStateControl
1394#define SB_PMIOA_REG8C 0x8C // StpClkHoldTime
1395#define SB_PMIOA_REG8E 0x8E // PopUpEndTime
1396#define SB_PMIOA_REG90 0x90 // C4Control
1397#define SB_PMIOA_REG94 0x94 // CStateTiming0
1398#define SB_PMIOA_REG98 0x98 // CStateTiming1
1399#define SB_PMIOA_REG9C 0x9C // C2Count
1400#define SB_PMIOA_REG9D 0x9D // C3Count
1401#define SB_PMIOA_REG9E 0x9E // C4Count
1402#define SB_PMIOA_REGA0 0xA0 // MessageCState
1403#define SB_PMIOA_REGA4 0xA4 //
1404#define SB_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
1405#define SB_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
1406#define SB_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
1407#define SB_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
1408#define SB_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
1409#define SB_PMIOA_REGB4 0xB4 // FidVidControl
1410#define SB_PMIOA_REGB6 0xB6 // TPRESET1
1411#define SB_PMIOA_REGB7 0xB7 // Tpreset1b
1412#define SB_PMIOA_REGB8 0xB8 // TPRESET2
1413#define SB_PMIOA_REGB9 0xB9 // Test0
1414#define SB_PMIOA_REGBA 0xBA // S_StateControl
1415#define SB_PMIOA_REGBC 0xBC // ThrottlingControl
1416#define SB_PMIOA_REGBE 0xBE // ResetControl
1417#define SB_PMIOA_REGBF 0xBF // ResetControl
1418#define SB_PMIOA_REGC0 0xC0 // S5Status
1419#define SB_PMIOA_REGC2 0xC2 // ResetStatus
1420#define SB_PMIOA_REGC4 0xC4 // ResetCommand
1421#define SB_PMIOA_REGC5 0xC5 // CF9Shadow
1422#define SB_PMIOA_REGC6 0xC6 // HTControl
1423#define SB_PMIOA_REGC8 0xC8 // Misc
1424#define SB_PMIOA_REGCC 0xCC // IoDrvSth
1425#define SB_PMIOA_REGD0 0xD0 // CLKRunEn
1426#define SB_PMIOA_REGD2 0xD2 // PmioDebug
1427#define SB_PMIOA_REGD6 0xD6 // IMCGating
1428#define SB_PMIOA_REGD8 0xD8 // MiscIndex
1429#define SB_PMIOA_REGD9 0xD9 // MiscData
1430#define SB_PMIOA_REGDA 0xDA // SataConfig
1431#define SB_PMIOA_REGDC 0xDC // HyperFlashConfig
1432#define SB_PMIOA_REGDE 0xDE // ABConfig
1433#define SB_PMIOA_REGE0 0xE0 // ABRegBar
1434#define SB_PMIOA_REGE6 0xE6 // FcEn
1435#define SB_PMIOA_REGEA 0xEA // PcibConfig
1436#define SB_PMIOA_REGEB 0xEB // AzEn
1437#define SB_PMIOA_REGEC 0xEC // LpcGating
1438#define SB_PMIOA_REGED 0xED // UsbGating
1439#define SB_PMIOA_REGEF 0xEF // UsbEnable
1440#define SB_PMIOA_REGF0 0xF0 // UsbControl
1441#define SB_PMIOA_REGF3 0xF3 // UsbDebug
1442#define SB_PMIOA_REGF6 0xF6 // GecEn
1443#define SB_PMIOA_REGF8 0xF8 // GecConfig
1444#define SB_PMIOA_REGFC 0xFC // TraceMemoryEn
1445
1446//
1447// SB800 SB MMIO Base (PMIO2)
1448// offset : 0x400
1449//
1450#define SB_PMIO2_REG00 0x00 // Fan0InputControl
1451#define SB_PMIO2_REG01 0x01 // Fan0Control
1452#define SB_PMIO2_REG02 0x02 // Fan0Freq
1453#define SB_PMIO2_REG03 0x03 // LowDuty0
1454#define SB_PMIO2_REG04 0x04 // MidDuty0
1455
1456#define SB_PMIO2_REG10 0x00 // Fan1InputControl
1457#define SB_PMIO2_REG11 0x01 // Fan1Control
1458#define SB_PMIO2_REG12 0x02 // Fan1Freq
1459#define SB_PMIO2_REG13 0x03 // LowDuty1
1460#define SB_PMIO2_REG14 0x04 // MidDuty1
1461
1462#define SB_PMIO2_REG 0xFC // TraceMemoryEn
1463
1464
1465//
1466// SB800 SB MMIO Base (GPIO/IoMux)
1467// offset : 0x100/0xD00
1468//
1469/*
1470GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
1471*/
1472#define SB_GPIO_REG00 0x00
1473#define SB_GPIO_REG32 0x20
1474#define SB_GPIO_REG33 0x21
1475#define SB_GPIO_REG34 0x22
1476#define SB_GPIO_REG35 0x23
1477#define SB_GPIO_REG36 0x24
1478#define SB_GPIO_REG37 0x25
1479#define SB_GPIO_REG38 0x26
1480#define SB_GPIO_REG39 0x27
1481#define SB_GPIO_REG40 0x28
1482#define SB_GPIO_REG41 0x29
1483#define SB_GPIO_REG42 0x2A
1484#define SB_GPIO_REG43 0x2B
1485#define SB_GPIO_REG44 0x2C
1486#define SB_GPIO_REG45 0x2D
1487#define SB_GPIO_REG46 0x2E
1488#define SB_GPIO_REG47 0x2F
1489#define SB_GPIO_REG48 0x30
1490#define SB_GPIO_REG49 0x31
1491#define SB_GPIO_REG50 0x32
1492#define SB_GPIO_REG51 0x33
1493#define SB_GPIO_REG52 0x34
1494#define SB_GPIO_REG53 0x35
1495#define SB_GPIO_REG54 0x36
1496#define SB_GPIO_REG55 0x37
1497#define SB_GPIO_REG56 0x38
1498#define SB_GPIO_REG57 0x39
1499#define SB_GPIO_REG58 0x3A
1500#define SB_GPIO_REG59 0x3B
1501#define SB_GPIO_REG60 0x3C
1502#define SB_GPIO_REG61 0x3D
1503#define SB_GPIO_REG62 0x3E
1504#define SB_GPIO_REG63 0x3F
1505#define SB_GPIO_REG64 0x40
1506#define SB_GPIO_REG65 0x41
1507#define SB_GPIO_REG66 0x42
1508#define SB_GPIO_REG67 0x43
1509
1510#define SB_GEVENT_REG00 0x60
1511#define SB_GEVENT_REG01 0x61
1512#define SB_GEVENT_REG02 0x62
1513#define SB_GEVENT_REG03 0x63
1514#define SB_GEVENT_REG04 0x64
1515#define SB_GEVENT_REG05 0x65
1516#define SB_GEVENT_REG06 0x66
1517#define SB_GEVENT_REG07 0x67
1518#define SB_GEVENT_REG08 0x68
1519#define SB_GEVENT_REG09 0x69
1520#define SB_GEVENT_REG10 0x6A
1521#define SB_GEVENT_REG11 0x6B
1522#define SB_GEVENT_REG12 0x6C
1523#define SB_GEVENT_REG13 0x6D
1524#define SB_GEVENT_REG14 0x6E
1525#define SB_GEVENT_REG15 0x6F
1526#define SB_GEVENT_REG16 0x70
1527#define SB_GEVENT_REG17 0x71
1528#define SB_GEVENT_REG18 0x72
1529#define SB_GEVENT_REG19 0x73
1530#define SB_GEVENT_REG20 0x74
1531#define SB_GEVENT_REG21 0x75
1532#define SB_GEVENT_REG22 0x76
1533#define SB_GEVENT_REG23 0x77
1534// S5-DOMAIN GPIO
1535#define SB_GPIO_REG160 0xA0
1536#define SB_GPIO_REG161 0xA1
1537#define SB_GPIO_REG162 0xA2
1538#define SB_GPIO_REG163 0xA3
1539#define SB_GPIO_REG164 0xA4
1540#define SB_GPIO_REG165 0xA5
1541#define SB_GPIO_REG166 0xA6
1542#define SB_GPIO_REG167 0xA7
1543#define SB_GPIO_REG168 0xA8
1544#define SB_GPIO_REG169 0xA9
1545#define SB_GPIO_REG170 0xAA
1546#define SB_GPIO_REG171 0xAB
1547#define SB_GPIO_REG172 0xAC
1548#define SB_GPIO_REG173 0xAD
1549#define SB_GPIO_REG174 0xAE
1550#define SB_GPIO_REG175 0xAF
1551#define SB_GPIO_REG176 0xB0
1552#define SB_GPIO_REG177 0xB1
1553#define SB_GPIO_REG178 0xB2
1554#define SB_GPIO_REG179 0xB3
1555#define SB_GPIO_REG180 0xB4
1556#define SB_GPIO_REG181 0xB5
1557#define SB_GPIO_REG182 0xB6
1558#define SB_GPIO_REG183 0xB7
1559#define SB_GPIO_REG184 0xB8
1560#define SB_GPIO_REG185 0xB9
1561#define SB_GPIO_REG186 0xBA
1562#define SB_GPIO_REG187 0xBB
1563#define SB_GPIO_REG188 0xBC
1564#define SB_GPIO_REG189 0xBD
1565#define SB_GPIO_REG190 0xBE
1566#define SB_GPIO_REG191 0xBF
1567#define SB_GPIO_REG192 0xC0
1568#define SB_GPIO_REG193 0xC1
1569#define SB_GPIO_REG194 0xC2
1570#define SB_GPIO_REG195 0xC3
1571#define SB_GPIO_REG196 0xC4
1572#define SB_GPIO_REG197 0xC5
1573#define SB_GPIO_REG198 0xC6
1574#define SB_GPIO_REG199 0xC7
1575#define SB_GPIO_REG200 0xC8
1576#define SB_GPIO_REG201 0xC9
1577#define SB_GPIO_REG202 0xCA
1578#define SB_GPIO_REG203 0xCB
1579#define SB_GPIO_REG204 0xCC
1580#define SB_GPIO_REG205 0xCD
1581#define SB_GPIO_REG206 0xCE
1582#define SB_GPIO_REG207 0xCF
1583#define SB_GPIO_REG208 0xD0
1584#define SB_GPIO_REG209 0xD1
1585#define SB_GPIO_REG210 0xD2
1586#define SB_GPIO_REG211 0xD3
1587#define SB_GPIO_REG212 0xD4
1588#define SB_GPIO_REG213 0xD5
1589#define SB_GPIO_REG214 0xD6
1590#define SB_GPIO_REG215 0xD7
1591#define SB_GPIO_REG216 0xD8
1592#define SB_GPIO_REG217 0xD9
1593#define SB_GPIO_REG218 0xDA
1594#define SB_GPIO_REG219 0xDB
1595#define SB_GPIO_REG220 0xDC
1596#define SB_GPIO_REG221 0xDD
1597#define SB_GPIO_REG222 0xDE
1598#define SB_GPIO_REG223 0xDF
1599#define SB_GPIO_REG224 0xF0
1600#define SB_GPIO_REG225 0xF1
1601#define SB_GPIO_REG226 0xF2
1602#define SB_GPIO_REG227 0xF3
1603#define SB_GPIO_REG228 0xF4
1604
1605//
1606// SB800 SB MMIO Base (SMBUS)
1607// offset : 0xA00
1608//
1609#define SB_SMBUS_REG12 0x12 // I2CbusConfig
1610
1611//
1612// SB800 SB MMIO Base (MISC)
1613// offset : 0xE00
1614//
1615#define SB_MISC_REG00 0x00 // ClkCntrl0
1616/*
1617SB_MISC_REG00 EQU 000h
1618 ClkCntrl0 EQU 0FFFFFFFFh
1619*/
1620#define SB_MISC_REG04 0x04 // ClkCntrl1
1621/*
1622SB_MISC_REG04 EQU 004h
1623 ClkCntrl1 EQU 0FFFFFFFFh
1624*/
1625#define SB_MISC_REG08 0x08 // ClkCntrl2
1626/*
1627SB_MISC_REG08 EQU 008h
1628 ClkCntrl2 EQU 0FFFFFFFFh
1629*/
1630#define SB_MISC_REG0C 0x0C // ClkCntrl3
1631/*
1632SB_MISC_REG0C EQU 00Ch
1633 ClkCntrl3 EQU 0FFFFFFFFh
1634*/
1635#define SB_MISC_REG10 0x10 // ClkCntrl4
1636/*
1637SB_MISC_REG10 EQU 010h
1638 ClkCntrl4 EQU 0FFFFFFFFh
1639*/
1640#define SB_MISC_REG14 0x14 // ClkCntrl5
1641/*
1642SB_MISC_REG14 EQU 014h
1643 ClkCntrl5 EQU 0FFFFFFFFh
1644*/
1645#define SB_MISC_REG18 0x18 // ClkCntrl6
1646/*
1647SB_MISC_REG18 EQU 018h
1648 ClkCntrl6 EQU 0FFFFFFFFh
1649*/
1650#define SB_MISC_REG30 0x30 // OscFreqCounter
1651/*
1652SB_MISC_REG30 EQU 030h
1653 OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
1654*/
1655#define SB_MISC_REG34 0x34 // HpetClkPeriod
1656/*
1657SB_MISC_REG34 EQU 034h
1658 HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
1659*/
1660#define SB_MISC_REG40 0x40 // MiscCntrl for clock only
1661/*
1662SB_MISC_REG40 EQU 040h
1663*/
1664
1665#define SB_MISC_REG80 0x80 /**< SB_MISC_REG80
1666 * @par
1667 * StrapStatus [15.0] - SB800 chip Strap Status
1668 * @li <b>0001</b> - Not USED FWH
1669 * @li <b>0002</b> - Not USED LPC ROM
1670 * @li <b>0004</b> - EC enabled
1671 * @li <b>0008</b> - Reserved
1672 * @li <b>0010</b> - Internal Clock mode
1673 */
1674
1675#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
1676#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
1677 // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
1678#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
1679#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
1680#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
1681
1682#define SB_MISC_REG84 0x84 // StrapOverride
1683/*
1684SB_MISC_REG84 EQU 084h
1685 Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
1686 Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
1687 Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
1688 Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
1689 Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
1690 Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
1691 Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
1692 Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
1693 Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
1694 Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
1695 Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin'
1696 PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ??
1697 BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin'
1698 ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
1699 BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
1700 StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
1701*/
1702#define SB_MISC_REGC0 0xC0 // CPU_Pstate0
1703/*
1704SB_MISC_REGC0 EQU 0C0h
1705 Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
1706 Core1_PState EQU BIT4+BIT5+BIT6
1707 Core2_PState EQU BIT8+BIT9+BIT10
1708 Core3_PState EQU BIT12+BIT13+BIT14
1709 Core4_PState EQU BIT16++BIT17+BIT18
1710 Core5_PState EQU BIT20+BIT21+BIT22
1711 Core6_PState EQU BIT24+BIT25+BIT26
1712 Core7_PState EQU BIT28+BIT29+BIT30
1713*/
1714#define SB_MISC_REGC4 0xC4 // CPU_Pstate1
1715/*
1716SB_MISC_REGC4 EQU 0C4h
1717 Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
1718 Core9_PState EQU BIT4+BIT5+BIT6
1719 Core10_PState EQU BIT8+BIT9+BIT10
1720 Core11_PState EQU BIT12+BIT13+BIT14
1721 Core12_PState EQU BIT16++BIT17+BIT18
1722 Core13_PState EQU BIT20+BIT21+BIT22
1723 Core14_PState EQU BIT24+BIT25+BIT26
1724 Core15_PState EQU BIT28+BIT29+BIT30
1725*/
1726#define SB_MISC_REGD0 0xD0 // CPU_Cstate0
1727/*
1728SB_MISC_REGD0 EQU 0D0h
1729 Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
1730 Core1_CState EQU BIT4+BIT5+BIT6
1731 Core2_CState EQU BIT8+BIT9+BIT10
1732 Core3_CState EQU BIT12+BIT13+BIT14
1733 Core4_CState EQU BIT16++BIT17+BIT18
1734 Core5_CState EQU BIT20+BIT21+BIT22
1735 Core6_CState EQU BIT24+BIT25+BIT26
1736 Core7_CState EQU BIT28+BIT29+BIT30
1737*/
1738#define SB_MISC_REGD4 0xD4 // CPU_Cstate1
1739/*
1740SB_MISC_REGD4 EQU 0D4h
1741 Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
1742 Core9_CState EQU BIT4+BIT5+BIT6
1743 Core10_CState EQU BIT8+BIT9+BIT10
1744 Core11_CState EQU BIT12+BIT13+BIT14
1745 Core12_CState EQU BIT16++BIT17+BIT18
1746 Core13_CState EQU BIT20+BIT21+BIT22
1747 Core14_CState EQU BIT24+BIT25+BIT26
1748 Core15_CState EQU BIT28+BIT29+BIT30
1749*/
1750#define SB_MISC_REGF0 0xF0 // SataPortSts ?? EC touch only
1751/*
1752SB_MISC_REGF0 EQU 0F0h
1753 Port0Sts EQU BIT0 ; The selected status of Port 0.
1754 Port1Sts EQU BIT1 ; The selected status of Port 1
1755 Port2Sts EQU BIT2 ; The selected status of Port 2.
1756 Port3Sts EQU BIT3 ; The selected status of Port 3
1757 Port4Sts EQU BIT4 ; The selected status of Port 4.
1758 Port5Sts EQU BIT5 ; The selected status of Port 5
1759 SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
1760 ; 01 - Select "delete" for Port 0 to 5
1761 ; 10 - Select "err" for Port 0 to 5
1762 ; 11 - Select "led" for Port 0 to 5
1763*/
1764
1765
1766
1767#define SB_RTC_REG00 0x00 // Seconds - RW
1768#define SB_RTC_REG01 0x01 // Seconds Alarm - RW
1769#define SB_RTC_REG02 0x02 // Minutes - RW
1770#define SB_RTC_REG03 0x03 // Minutes Alarm - RW
1771#define SB_RTC_REG04 0x04 // ours - RW
1772#define SB_RTC_REG05 0x05 // ours Alarm- RW
1773#define SB_RTC_REG06 0x06 // Day of Week - RW
1774#define SB_RTC_REG07 0x07 // Date of Mont - RW
1775#define SB_RTC_REG08 0x08 // Mont - RW
1776#define SB_RTC_REG09 0x09 // Year - RW
1777#define SB_RTC_REG0A 0x0A // Register A - RW
1778#define SB_RTC_REG0B 0x0B // Register B - RW
1779#define SB_RTC_REG0C 0x0C // Register C - R
1780#define SB_RTC_REG0D 0x0D // DateAlarm - RW
1781#define SB_RTC_REG32 0x32 // AltCentury - RW
1782#define SB_RTC_REG48 0x48 // Century - RW
1783#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW
1784#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW
1785#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW
1786#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW
1787
1788#define SB_ECMOS_REG00 0x00 // scratch - reg
1789//;BIT0=0 AsicDebug is enabled
1790//;BIT1=0 SLT S3 runs
1791#define SB_ECMOS_REG01 0x01
1792#define SB_ECMOS_REG02 0x02
1793#define SB_ECMOS_REG03 0x03
1794#define SB_ECMOS_REG04 0x04
1795#define SB_ECMOS_REG05 0x05
1796#define SB_ECMOS_REG06 0x06
1797#define SB_ECMOS_REG07 0x07
1798#define SB_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
1799#define SB_ECMOS_REG09 0x09
1800#define SB_ECMOS_REG0A 0x0A
1801#define SB_ECMOS_REG0B 0x0B
1802
1803#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID
1804#define SB_ECMOS_REG0D 0x0D //;Reserve for NB
1805
1806#define SB_IOMAP_REG00 0x000 // Dma_C 0
1807#define SB_IOMAP_REG02 0x002 // Dma_C 1
1808#define SB_IOMAP_REG04 0x004 // Dma_C 2
1809#define SB_IOMAP_REG06 0x006 // Dma_C 3
1810#define SB_IOMAP_REG08 0x008 // Dma_Status
1811#define SB_IOMAP_REG09 0x009 // Dma_WriteRest
1812#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask
1813#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode
1814#define SB_IOMAP_REG0C 0x00C // Dma_Clear
1815#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr
1816#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask
1817#define SB_IOMAP_REG0F 0x00F // Dma_AllMask
1818#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1
1819#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2
1820#define SB_IOMAP_REG40 0x040 // TimerC0
1821#define SB_IOMAP_REG41 0x041 // TimerC1
1822#define SB_IOMAP_REG42 0x042 // TimerC2
1823#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord
1824#define SB_IOMAP_REG61 0x061 // Nmi_Status
1825#define SB_IOMAP_REG70 0x070 // Nmi_Enable
1826#define SB_IOMAP_REG71 0x071 // RtcDataPort
1827#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort
1828#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort
1829#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0
1830#define SB_IOMAP_REG81 0x081 // Dma_PageC2
1831#define SB_IOMAP_REG82 0x082 // Dma_PageC3
1832#define SB_IOMAP_REG83 0x083 // Dma_PageC1
1833#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1
1834#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2
1835#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3
1836#define SB_IOMAP_REG87 0x087 // Dma_PageC0
1837#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4
1838#define SB_IOMAP_REG89 0x089 // Dma_PageC6
1839#define SB_IOMAP_REG8A 0x08A // Dma_PageC7
1840#define SB_IOMAP_REG8B 0x08B // Dma_PageC5
1841#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
1842#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
1843#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
1844#define SB_IOMAP_REG8F 0x08F // Dma_Refres
1845#define SB_IOMAP_REG92 0x092 // FastInit
1846#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
1847#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
1848#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
1849#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
1850#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
1851#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
1852#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
1853#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
1854#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr
1855#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
1856#define SB_IOMAP_REGD0 0x0D0 // Dma_Status
1857#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest
1858#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask
1859#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode
1860#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear
1861#define SB_IOMAP_REGDA 0x0DA // Dma_Clear
1862#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask
1863#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask
1864#define SB_IOMAP_REGF0 0x0F0 // NCP_Error
1865#define SB_IOMAP_REG40B 0x040B // DMA1_Extend
1866#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
1867#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend
1868#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
1869#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
1870#define SB_IOMAP_REGC14 0x0C14 // Pci_Error
1871#define SB_IOMAP_REGC50 0x0C50 // CMIndex
1872#define SB_IOMAP_REGC51 0x0C51 // CMData
1873#define SB_IOMAP_REGC52 0x0C52 // GpmPort
1874#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc
1875#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index
1876#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data
1877#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
1878#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
1879#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index
1880#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data
1881#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
1882
1883
1884#define SB_SPI_MMIO_REG00 0x00 //SPI_
1885#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
1886
1887#define AMD_NB_REG78 0x78
1888#define AMD_NB_SCRATCH AMD_NB_REG78
1889#define MailBoxPort 0x3E
1890
1891// GPP Link Configuration
1892#define GPP_CFGMODE_X4000 0x0
1893#define GPP_CFGMODE_X2200 0x2
1894#define GPP_CFGMODE_X2110 0x3
1895#define GPP_CFGMODE_X1111 0x4
1896
1897#define MAX_TRAINING_RETRY 0x4000
1898#define MAX_GPP_RESETS 8 //lx-temp to confirm with jason
1899
1900
1901#pragma pack (pop)
1902