blob: c407537301482a688d764cebe05f37f04ca9d179 [file] [log] [blame]
Frank Vibrans2b4c8312011-02-14 18:30:54 +00001
2/**
3 * @file
4 *
5 * Config Southbridge EC Controller
6 *
7 * Init EC features.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: CIMx-SB
11 * @e sub-project:
12 * @e \$Revision:$ @e \$Date:$
13 *
14 */
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghanef5981b2014-07-06 19:20:52 +100020 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000021 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghanef5981b2014-07-06 19:20:52 +100028 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +000030 * from this software without specific prior written permission.
Edward O'Callaghanef5981b2014-07-06 19:20:52 +100031 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000032 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghanef5981b2014-07-06 19:20:52 +100042 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000043 * ***************************************************************************
44 *
45 */
46
47#include "SBPLATFORM.h"
48#include "cbtypes.h"
49
50#ifndef NO_EC_SUPPORT
51
52/**
53 * Config EC controller during power-on
54 *
55 *
56 *
57 * @param[in] pConfig Southbridge configuration structure pointer.
58 *
59 */
60VOID
61ecPowerOnInit (
62 IN AMDSBCFG* pConfig
63 )
64{
65 //Enable config mode
66 EnterEcConfig ();
67
68 //Do settings for mailbox - logical device 0x09
69 RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
70 RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
71 RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
72 RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
73
Kerry She991f8802011-06-01 01:56:49 +000074 if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
Frank Vibrans2b4c8312011-02-14 18:30:54 +000075 //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
76 RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
77
78 //Disable LPC Decoding of port 60/64
79 RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
80
81 //Enable logical device 0x07 (Keyboard controller)
82 RWEC8 (0x07, 0x00, 0x07);
83 RWEC8 (0x30, 0x00, 0x01);
84 }
85
Kerry She991f8802011-06-01 01:56:49 +000086 if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
Frank Vibrans2b4c8312011-02-14 18:30:54 +000087 //Logical device 0x03
88 RWEC8 (0x07, 0x00, 0x03);
89 RWEC8 (0x60, 0x00, 0x00);
90 RWEC8 (0x61, 0x00, 0x62);
91 RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8
92 }
93
94 //Enable EC (IMC) to generate SMI to BIOS
95 RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
96 ExitEcConfig ();
97}
98
99/**
100 * Config EC controller before PCI emulation
101 *
102 *
103 *
104 * @param[in] pConfig Southbridge configuration structure pointer.
105 *
106 */
107VOID
108ecInitBeforePciEnum (
109 IN AMDSBCFG* pConfig
110 )
111{
Arthur Heymans2fe01262022-03-23 21:46:17 +0100112 /* AMDSBCFG* pTmp; // dummy code */
113 /* pTmp = pConfig; */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000114}
115
116/**
117 * Prepare EC controller to boot to OS.
118 *
119 *
120 * @param[in] pConfig Southbridge configuration structure pointer.
121 *
122 */
123VOID
124ecInitLatePost (
125 IN AMDSBCFG* pConfig
126 )
127{
Arthur Heymans2fe01262022-03-23 21:46:17 +0100128 /* AMDSBCFG* pTmp; // dummy code */
129 /* pTmp = pConfig; */
Frank Vibrans2b4c8312011-02-14 18:30:54 +0000130}
131#endif