commit 991f8808933a8b528108dcd48a029ebf40b05c6b
author Kerry She <kerry.she@amd.com> Wed Jun 01 01:56:49 2011 +0000
committer Kerry She <Kerry.She@amd.com> Wed Jun 01 01:56:49 2011 +0000
tree d08e8791ab01d76df137a984f0fed1a91cab5632
parent b2ecd8151481af7c5a74ed61967ad9698486253e

This patch fix a AMD sb800 wrapper compile warning:
 src/southbridge/amd/cimx_wrapper/sb800/late
 call clear_ioapic but not include the prototype declare header file.

Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/vendorcode/amd/cimx/sb800/EC.c

diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c
index 220424f..633d251 100644
--- a/src/vendorcode/amd/cimx/sb800/EC.c
+++ b/src/vendorcode/amd/cimx/sb800/EC.c
@@ -71,7 +71,7 @@
   RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF));  //set LSB of Mailbox port
   RWEC8 (0x30, 0x00, 0x01);               //;Enable Mailbox Registers Interface, bit0=1
 
-  if ( pConfig->BuildParameters.EcKbd == ENABLED) {
+  if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) {
     //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
 
@@ -83,7 +83,7 @@
     RWEC8 (0x30, 0x00, 0x01);
   }
 
-  if ( pConfig->BuildParameters.EcChannel0 == ENABLED) {
+  if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) {
     //Logical device 0x03
     RWEC8 (0x07, 0x00, 0x03);
     RWEC8 (0x60, 0x00, 0x00);