Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 3 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 4 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Elyes HAOUAS | 46c5807 | 2019-04-28 18:17:17 +0200 | [diff] [blame] | 6 | #include <cf9_reset.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <delay.h> |
Nicola Corna | 14604da | 2018-05-15 17:15:03 +0200 | [diff] [blame] | 9 | #include <device/pci_def.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 10 | #include <halt.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 11 | #include <string.h> |
Nathaniel Roach | 52f0871 | 2017-09-09 19:58:08 +0800 | [diff] [blame] | 12 | #include <timestamp.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 13 | #include "me.h" |
| 14 | #include "pch.h" |
| 15 | |
| 16 | static const char *me_ack_values[] = { |
| 17 | [ME_HFS_ACK_NO_DID] = "No DID Ack received", |
| 18 | [ME_HFS_ACK_RESET] = "Non-power cycle reset", |
| 19 | [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", |
| 20 | [ME_HFS_ACK_S3] = "Go to S3", |
| 21 | [ME_HFS_ACK_S4] = "Go to S4", |
| 22 | [ME_HFS_ACK_S5] = "Go to S5", |
| 23 | [ME_HFS_ACK_GBL_RESET] = "Global Reset", |
| 24 | [ME_HFS_ACK_CONTINUE] = "Continue to boot" |
| 25 | }; |
| 26 | |
| 27 | static inline void pci_read_dword_ptr(void *ptr, int offset) |
| 28 | { |
| 29 | u32 dword = pci_read_config32(PCH_ME_DEV, offset); |
| 30 | memcpy(ptr, &dword, sizeof(dword)); |
| 31 | } |
| 32 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 33 | void intel_early_me_status(void) |
| 34 | { |
| 35 | struct me_hfs hfs; |
| 36 | struct me_gmes gmes; |
Nicola Corna | 14604da | 2018-05-15 17:15:03 +0200 | [diff] [blame] | 37 | u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 38 | |
Nicola Corna | 14604da | 2018-05-15 17:15:03 +0200 | [diff] [blame] | 39 | if ((id == 0xffffffff) || (id == 0x00000000) || |
| 40 | (id == 0x0000ffff) || (id == 0xffff0000)) { |
| 41 | printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n"); |
| 42 | } else { |
| 43 | pci_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 44 | pci_read_dword_ptr(&gmes, PCI_ME_GMES); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 45 | |
Nicola Corna | 14604da | 2018-05-15 17:15:03 +0200 | [diff] [blame] | 46 | intel_me_status(&hfs, &gmes); |
| 47 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | int intel_early_me_init(void) |
| 51 | { |
| 52 | int count; |
| 53 | struct me_uma uma; |
| 54 | struct me_hfs hfs; |
| 55 | |
| 56 | printk(BIOS_INFO, "Intel ME early init\n"); |
| 57 | |
| 58 | /* Wait for ME UMA SIZE VALID bit to be set */ |
| 59 | for (count = ME_RETRY; count > 0; --count) { |
| 60 | pci_read_dword_ptr(&uma, PCI_ME_UMA); |
| 61 | if (uma.valid) |
| 62 | break; |
| 63 | udelay(ME_DELAY); |
| 64 | } |
| 65 | if (!count) { |
| 66 | printk(BIOS_ERR, "ERROR: ME is not ready!\n"); |
| 67 | return -1; |
| 68 | } |
| 69 | |
| 70 | /* Check for valid firmware */ |
| 71 | pci_read_dword_ptr(&hfs, PCI_ME_HFS); |
| 72 | if (hfs.fpt_bad) { |
| 73 | printk(BIOS_WARNING, "WARNING: ME has bad firmware\n"); |
| 74 | return -1; |
| 75 | } |
| 76 | |
| 77 | printk(BIOS_INFO, "Intel ME firmware is ready\n"); |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | int intel_early_me_uma_size(void) |
| 82 | { |
| 83 | struct me_uma uma; |
| 84 | |
| 85 | pci_read_dword_ptr(&uma, PCI_ME_UMA); |
| 86 | if (uma.valid) { |
| 87 | printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size); |
| 88 | return uma.size; |
| 89 | } |
| 90 | |
| 91 | printk(BIOS_DEBUG, "ME: Invalid UMA size\n"); |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static inline void set_global_reset(int enable) |
| 96 | { |
| 97 | u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); |
| 98 | |
| 99 | /* Clear CF9 Without Resume Well Reset Enable */ |
| 100 | etr3 &= ~ETR3_CWORWRE; |
| 101 | |
| 102 | /* CF9GR indicates a Global Reset */ |
| 103 | if (enable) |
| 104 | etr3 |= ETR3_CF9GR; |
| 105 | else |
| 106 | etr3 &= ~ETR3_CF9GR; |
| 107 | |
| 108 | pci_write_config32(PCH_LPC_DEV, ETR3, etr3); |
| 109 | } |
| 110 | |
| 111 | int intel_early_me_init_done(u8 status) |
| 112 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 113 | u8 reset, errorcode, opmode; |
| 114 | u16 reg16; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 115 | u32 mebase_l, mebase_h; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 116 | u32 millisec; |
| 117 | u32 hfs, me_fws2; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 118 | struct me_did did = { |
| 119 | .init_done = ME_INIT_DONE, |
| 120 | .status = status |
| 121 | }; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 122 | u32 meDID; |
| 123 | |
| 124 | hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xff000) >> 12; |
| 125 | |
| 126 | opmode = (hfs & 0xf0) >> 4; |
| 127 | errorcode = hfs & 0xf; |
| 128 | |
| 129 | if (opmode != ME_HFS_MODE_NORMAL) { |
| 130 | printk(BIOS_NOTICE, "ME: Wrong mode : %d\n", opmode); |
| 131 | //return 0; |
| 132 | } |
| 133 | if (errorcode) { |
| 134 | printk(BIOS_NOTICE, "ME: HFS error : %d\n", errorcode); |
| 135 | //return 0; |
| 136 | } |
| 137 | |
| 138 | me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); |
| 139 | printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); |
| 140 | printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); |
| 141 | printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); |
| 142 | printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); |
| 143 | printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); |
| 144 | printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5); |
| 145 | printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6); |
| 146 | printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7); |
| 147 | printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8); |
| 148 | printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9); |
| 149 | printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11); |
| 150 | printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12); |
| 151 | printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16); |
| 152 | printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); |
| 153 | printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); |
| 154 | |
Elyes HAOUAS | 1bcd7fc | 2016-07-28 21:20:04 +0200 | [diff] [blame] | 155 | // Poll CPU replaced for 50ms |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 156 | millisec = 0; |
| 157 | while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) { |
| 158 | udelay(1000); |
| 159 | me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); |
| 160 | millisec++; |
| 161 | } |
| 162 | if (millisec >= 50 || ((me_fws2 & 0x100) >> 8) == 0x0) { |
| 163 | printk(BIOS_NOTICE, "Waited long enough, or CPU was not replaced, continue...\n"); |
| 164 | } else if ((me_fws2 & 0x100) == 0x100) { |
| 165 | if ((me_fws2 & 0x80) == 0x80) { |
| 166 | printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 167 | reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; |
| 168 | pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 169 | set_global_reset(0); |
Elyes HAOUAS | 46c5807 | 2019-04-28 18:17:17 +0200 | [diff] [blame] | 170 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) { |
| 174 | printk(BIOS_NOTICE, "Full training required\n"); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | printk(BIOS_NOTICE, "PASSED! Tell ME that DRAM is ready\n"); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 179 | |
| 180 | /* MEBASE from MESEG_BASE[35:20] */ |
| 181 | mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L); |
| 182 | mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf; |
| 183 | did.uma_base = (mebase_l >> 20) | (mebase_h << 12); |
| 184 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 185 | meDID = did.uma_base | (1 << 28);// | (1 << 23); |
| 186 | pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 187 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 188 | /* Must wait for ME acknowledgement */ |
Nathaniel Roach | d7e0cb9 | 2017-09-09 19:59:07 +0800 | [diff] [blame] | 189 | if (opmode == ME_HFS_MODE_DEBUG) { |
| 190 | printk(BIOS_NOTICE, |
| 191 | "ME: ME is reporting as disabled, " |
| 192 | "so not waiting for a response.\n"); |
| 193 | } else { |
| 194 | timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); |
| 195 | udelay(100); |
| 196 | millisec = 0; |
| 197 | do { |
| 198 | udelay(1000); |
| 199 | hfs = (pci_read_config32( |
| 200 | PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) |
| 201 | >> 24; |
| 202 | millisec++; |
| 203 | } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) |
| 204 | && (millisec <= 5000)); |
| 205 | timestamp_add_now(TS_ME_INFORM_DRAM_DONE); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 206 | } |
Nathaniel Roach | d7e0cb9 | 2017-09-09 19:59:07 +0800 | [diff] [blame] | 207 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 208 | |
| 209 | me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); |
| 210 | printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); |
| 211 | printk(BIOS_NOTICE, "ME: Bist in progress: 0x%x\n", me_fws2 & 0x1); |
| 212 | printk(BIOS_NOTICE, "ME: ICC Status : 0x%x\n", (me_fws2 & 0x6) >> 1); |
| 213 | printk(BIOS_NOTICE, "ME: Invoke MEBx : 0x%x\n", (me_fws2 & 0x8) >> 3); |
| 214 | printk(BIOS_NOTICE, "ME: CPU replaced : 0x%x\n", (me_fws2 & 0x10) >> 4); |
| 215 | printk(BIOS_NOTICE, "ME: MBP ready : 0x%x\n", (me_fws2 & 0x20) >> 5); |
| 216 | printk(BIOS_NOTICE, "ME: MFS failure : 0x%x\n", (me_fws2 & 0x40) >> 6); |
| 217 | printk(BIOS_NOTICE, "ME: Warm reset req : 0x%x\n", (me_fws2 & 0x80) >> 7); |
| 218 | printk(BIOS_NOTICE, "ME: CPU repl valid : 0x%x\n", (me_fws2 & 0x100) >> 8); |
| 219 | printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0x600) >> 9); |
| 220 | printk(BIOS_NOTICE, "ME: FW update req : 0x%x\n", (me_fws2 & 0x800) >> 11); |
| 221 | printk(BIOS_NOTICE, "ME: (Reserved) : 0x%x\n", (me_fws2 & 0xf000) >> 12); |
| 222 | printk(BIOS_NOTICE, "ME: Current state : 0x%x\n", (me_fws2 & 0xff0000) >> 16); |
| 223 | printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); |
| 224 | printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); |
| 225 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 226 | |
| 227 | /* Return the requested BIOS action */ |
| 228 | printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 229 | me_ack_values[(hfs & 0xe) >> 1]); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 230 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 231 | reset = inb(0xcf9); |
| 232 | reset &= 0xf1; |
| 233 | switch ((hfs & 0xe) >> 1) { |
| 234 | case ME_HFS_ACK_NO_DID: |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 235 | case ME_HFS_ACK_CONTINUE: |
| 236 | /* Continue to boot */ |
| 237 | return 0; |
| 238 | case ME_HFS_ACK_RESET: |
| 239 | /* Non-power cycle reset */ |
| 240 | set_global_reset(0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 241 | reset |= 0x06; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 242 | break; |
| 243 | case ME_HFS_ACK_PWR_CYCLE: |
| 244 | /* Power cycle reset */ |
| 245 | set_global_reset(0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 246 | reset |= 0x0e; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 247 | break; |
| 248 | case ME_HFS_ACK_GBL_RESET: |
| 249 | /* Global reset */ |
| 250 | set_global_reset(1); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 251 | reset |= 0x0e; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 252 | break; |
| 253 | case ME_HFS_ACK_S3: |
| 254 | case ME_HFS_ACK_S4: |
| 255 | case ME_HFS_ACK_S5: |
| 256 | break; |
| 257 | } |
| 258 | |
| 259 | /* Perform the requested reset */ |
| 260 | if (reset) { |
| 261 | outb(reset, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 262 | halt(); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 263 | } |
| 264 | return -1; |
| 265 | } |