Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 3 | |
| 4 | /* Intel Cougar Point PCH support */ |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 5 | #include <southbridge/intel/bd82x6x/pch.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 6 | |
| 7 | Scope(\) |
| 8 | { |
| 9 | // IO-Trap at 0x800. This is the ACPI->SMI communication interface. |
| 10 | |
| 11 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 12 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 13 | { |
| 14 | Offset(0x8), |
| 15 | TRP0, 8 // IO-Trap at 0x808 |
| 16 | } |
| 17 | |
| 18 | // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) |
| 19 | OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) |
| 20 | Field(PMIO, ByteAcc, NoLock, Preserve) |
| 21 | { |
| 22 | Offset(0x20), // GPE0_STS |
| 23 | , 16, |
| 24 | GS00, 1, // GPIO00 SCI/Wake Status |
| 25 | GS01, 1, // GPIO01 SCI/Wake Status |
| 26 | GS02, 1, // GPIO02 SCI/Wake Status |
| 27 | GS03, 1, // GPIO03 SCI/Wake Status |
| 28 | GS04, 1, // GPIO04 SCI/Wake Status |
| 29 | GS05, 1, // GPIO05 SCI/Wake Status |
| 30 | GS06, 1, // GPIO06 SCI/Wake Status |
| 31 | GS07, 1, // GPIO07 SCI/Wake Status |
| 32 | GS08, 1, // GPIO08 SCI/Wake Status |
| 33 | GS09, 1, // GPIO09 SCI/Wake Status |
| 34 | GS10, 1, // GPIO10 SCI/Wake Status |
| 35 | GS11, 1, // GPIO11 SCI/Wake Status |
| 36 | GS12, 1, // GPIO12 SCI/Wake Status |
| 37 | GS13, 1, // GPIO13 SCI/Wake Status |
| 38 | GS14, 1, // GPIO14 SCI/Wake Status |
| 39 | GS15, 1, // GPIO15 SCI/Wake Status |
| 40 | Offset(0x28), // GPE0_EN |
| 41 | , 16, |
| 42 | GE00, 1, // GPIO00 SCI/Wake Enable |
| 43 | GE01, 1, // GPIO01 SCI/Wake Enable |
| 44 | GE02, 1, // GPIO02 SCI/Wake Enable |
| 45 | GE03, 1, // GPIO03 SCI/Wake Enable |
| 46 | GE04, 1, // GPIO04 SCI/Wake Enable |
| 47 | GE05, 1, // GPIO05 SCI/Wake Enable |
| 48 | GE06, 1, // GPIO06 SCI/Wake Enable |
| 49 | GE07, 1, // GPIO07 SCI/Wake Enable |
| 50 | GE08, 1, // GPIO08 SCI/Wake Enable |
| 51 | GE09, 1, // GPIO09 SCI/Wake Enable |
| 52 | GE10, 1, // GPIO10 SCI/Wake Enable |
| 53 | GE11, 1, // GPIO11 SCI/Wake Enable |
| 54 | GE12, 1, // GPIO12 SCI/Wake Enable |
| 55 | GE13, 1, // GPIO13 SCI/Wake Enable |
| 56 | GE14, 1, // GPIO14 SCI/Wake Enable |
| 57 | GE15, 1, // GPIO15 SCI/Wake Enable |
| 58 | Offset(0x42), // General Purpose Control |
| 59 | , 1, // skip 1 bit |
| 60 | GPEC, 1, // SWGPE_CTRL |
| 61 | } |
| 62 | |
| 63 | // GPIO IO mapped registers (0x1f.0 reg 0x48.l) |
| 64 | OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) |
| 65 | Field(GPIO, ByteAcc, NoLock, Preserve) |
| 66 | { |
| 67 | Offset(0x00), // GPIO Use Select |
| 68 | GU00, 8, |
| 69 | GU01, 8, |
| 70 | GU02, 8, |
| 71 | GU03, 8, |
| 72 | Offset(0x04), // GPIO IO Select |
| 73 | GIO0, 8, |
| 74 | GIO1, 8, |
| 75 | GIO2, 8, |
| 76 | GIO3, 8, |
| 77 | Offset(0x0c), // GPIO Level |
Arthur Heymans | 5493b45 | 2018-12-23 18:40:15 +0100 | [diff] [blame] | 78 | GP00, 1, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 79 | GP01, 1, |
| 80 | GP02, 1, |
Paul Menzel | eb4920d | 2014-04-10 19:50:58 +0200 | [diff] [blame] | 81 | GP03, 1, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 82 | GP04, 1, |
| 83 | GP05, 1, |
| 84 | GP06, 1, |
| 85 | GP07, 1, |
| 86 | GP08, 1, |
| 87 | GP09, 1, |
| 88 | GP10, 1, |
| 89 | GP11, 1, |
| 90 | GP12, 1, |
| 91 | GP13, 1, |
| 92 | GP14, 1, |
| 93 | GP15, 1, |
| 94 | GP16, 1, |
| 95 | GP17, 1, |
| 96 | GP18, 1, |
| 97 | GP19, 1, |
| 98 | GP20, 1, |
| 99 | GP21, 1, |
| 100 | GP22, 1, |
| 101 | GP23, 1, |
| 102 | GP24, 1, |
| 103 | GP25, 1, |
| 104 | GP26, 1, |
| 105 | GP27, 1, |
| 106 | GP28, 1, |
| 107 | GP29, 1, |
| 108 | GP30, 1, |
| 109 | GP31, 1, |
| 110 | Offset(0x18), // GPIO Blink |
| 111 | GB00, 8, |
| 112 | GB01, 8, |
| 113 | GB02, 8, |
| 114 | GB03, 8, |
| 115 | Offset(0x2c), // GPIO Invert |
| 116 | GIV0, 8, |
| 117 | GIV1, 8, |
| 118 | GIV2, 8, |
| 119 | GIV3, 8, |
| 120 | Offset(0x30), // GPIO Use Select 2 |
| 121 | GU04, 8, |
| 122 | GU05, 8, |
| 123 | GU06, 8, |
| 124 | GU07, 8, |
| 125 | Offset(0x34), // GPIO IO Select 2 |
| 126 | GIO4, 8, |
| 127 | GIO5, 8, |
| 128 | GIO6, 8, |
| 129 | GIO7, 8, |
| 130 | Offset(0x38), // GPIO Level 2 |
| 131 | GP32, 1, |
| 132 | GP33, 1, |
| 133 | GP34, 1, |
| 134 | GP35, 1, |
| 135 | GP36, 1, |
| 136 | GP37, 1, |
| 137 | GP38, 1, |
| 138 | GP39, 1, |
| 139 | GP40, 1, |
| 140 | GP41, 1, |
| 141 | GP42, 1, |
| 142 | GP43, 1, |
| 143 | GP44, 1, |
| 144 | GP45, 1, |
| 145 | GP46, 1, |
| 146 | GP47, 1, |
| 147 | GP48, 1, |
| 148 | GP49, 1, |
| 149 | GP50, 1, |
| 150 | GP51, 1, |
| 151 | GP52, 1, |
| 152 | GP53, 1, |
| 153 | GP54, 1, |
| 154 | GP55, 1, |
| 155 | GP56, 1, |
| 156 | GP57, 1, |
| 157 | GP58, 1, |
| 158 | GP59, 1, |
| 159 | GP60, 1, |
| 160 | GP61, 1, |
| 161 | GP62, 1, |
| 162 | GP63, 1, |
| 163 | Offset(0x40), // GPIO Use Select 3 |
| 164 | GU08, 8, |
| 165 | GU09, 4, |
| 166 | Offset(0x44), // GPIO IO Select 3 |
| 167 | GIO8, 8, |
| 168 | GIO9, 4, |
| 169 | Offset(0x48), // GPIO Level 3 |
| 170 | GP64, 1, |
| 171 | GP65, 1, |
| 172 | GP66, 1, |
| 173 | GP67, 1, |
| 174 | GP68, 1, |
| 175 | GP69, 1, |
| 176 | GP70, 1, |
| 177 | GP71, 1, |
| 178 | GP72, 1, |
| 179 | GP73, 1, |
| 180 | GP74, 1, |
| 181 | GP75, 1, |
| 182 | } |
| 183 | |
| 184 | |
| 185 | // ICH7 Root Complex Register Block. Memory Mapped through RCBA) |
| 186 | OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) |
| 187 | Field(RCRB, DWordAcc, Lock, Preserve) |
| 188 | { |
| 189 | Offset(0x0000), // Backbone |
| 190 | Offset(0x1000), // Chipset |
| 191 | Offset(0x3000), // Legacy Configuration Registers |
| 192 | Offset(0x3404), // High Performance Timer Configuration |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 193 | HPAS, 2, // Address Select |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 194 | , 5, |
| 195 | HPTE, 1, // Address Enable |
| 196 | Offset(0x3418), // FD (Function Disable) |
Duncan Laurie | c323036 | 2012-04-27 09:55:45 -0700 | [diff] [blame] | 197 | , 1, // Reserved |
| 198 | PCID, 1, // PCI bridge disable |
| 199 | SA1D, 1, // SATA1 disable |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 200 | SMBD, 1, // SMBUS disable |
| 201 | HDAD, 1, // Azalia disable |
Duncan Laurie | c323036 | 2012-04-27 09:55:45 -0700 | [diff] [blame] | 202 | , 8, // Reserved |
| 203 | EH2D, 1, // EHCI #2 disable |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 204 | LPBD, 1, // LPC bridge disable |
Duncan Laurie | c323036 | 2012-04-27 09:55:45 -0700 | [diff] [blame] | 205 | EH1D, 1, // EHCI #1 disable |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 206 | RP1D, 1, // Root Port 1 disable |
| 207 | RP2D, 1, // Root Port 2 disable |
| 208 | RP3D, 1, // Root Port 3 disable |
Duncan Laurie | c323036 | 2012-04-27 09:55:45 -0700 | [diff] [blame] | 209 | RP4D, 1, // Root Port 4 disable |
| 210 | RP5D, 1, // Root Port 5 disable |
| 211 | RP6D, 1, // Root Port 6 disable |
| 212 | RP7D, 1, // Root Port 7 disable |
| 213 | RP8D, 1, // Root Port 8 disable |
| 214 | TTRD, 1, // Thermal sensor registers disable |
| 215 | SA2D, 1, // SATA2 disable |
| 216 | Offset(0x3428), // FD2 (Function Disable 2) |
| 217 | BDFD, 1, // Display BDF |
| 218 | ME1D, 1, // ME Interface 1 disable |
| 219 | ME2D, 1, // ME Interface 2 disable |
| 220 | IDRD, 1, // IDE redirect disable |
| 221 | KTCT, 1, // Keyboard Text redirect disable |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 222 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | // High Definition Audio (Azalia) 0:1b.0 |
| 226 | #include "audio.asl" |
| 227 | |
| 228 | // PCI Express Ports 0:1c.x |
Arthur Heymans | cd36634 | 2018-12-30 12:49:21 +0100 | [diff] [blame] | 229 | #include <southbridge/intel/common/acpi/pcie.asl> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 230 | |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 231 | // USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 232 | #include "usb.asl" |
| 233 | |
| 234 | // LPC Bridge 0:1f.0 |
| 235 | #include "lpc.asl" |
| 236 | |
| 237 | // SATA 0:1f.2, 0:1f.5 |
| 238 | #include "sata.asl" |
| 239 | |
| 240 | // SMBus 0:1f.3 |
Elyes HAOUAS | 085ab5a | 2019-10-31 10:12:02 +0100 | [diff] [blame] | 241 | #include <southbridge/intel/common/acpi/smbus.asl> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 242 | |
| 243 | Method (_OSC, 4) |
| 244 | { |
Martin Roth | a34b5bc | 2018-05-06 21:06:18 -0500 | [diff] [blame] | 245 | /* |
| 246 | * Arg0 - A Buffer containing a UUID |
| 247 | * Arg1 - An Integer containing a Revision ID of the buffer format |
| 248 | * Arg2 - An Integer containing a count of entries in Arg3 |
| 249 | * Arg3 - A Buffer containing a list of DWORD capabilities |
| 250 | */ |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 251 | /* Check for XHCI */ |
| 252 | If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) |
| 253 | { |
Martin Roth | a34b5bc | 2018-05-06 21:06:18 -0500 | [diff] [blame] | 254 | Return (^XHC.POSC(Arg2, Arg3)) |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | /* Check for PCIe */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 258 | If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 259 | { |
| 260 | /* Let OS control everything */ |
| 261 | Return (Arg3) |
| 262 | } |
Marc Jones | e7ae96f | 2012-11-13 15:07:45 -0700 | [diff] [blame] | 263 | |
| 264 | /* Else Return Unrecognized UUID */ |
| 265 | CreateDWordField (Arg3, 0, CDW1) |
| 266 | Or (CDW1, 4, CDW1) |
| 267 | Return (Arg3) |
| 268 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 269 | } |