Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
| 5 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 17 | #include <cpu/cpu.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 18 | #include <cpu/x86/mp.h> |
| 19 | #include <cpu/x86/mtrr.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 20 | #include <cpu/x86/msr.h> |
| 21 | #include <cpu/amd/amdfam15.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/cpu.h> |
| 25 | #include <soc/northbridge.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 26 | #include <soc/smi.h> |
Marshall Dawson | 0814b12 | 2018-01-10 11:35:24 -0700 | [diff] [blame] | 27 | #include <soc/iomap.h> |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 28 | #include <console/console.h> |
| 29 | |
| 30 | /* |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 31 | * MP and SMM loading initialization. |
| 32 | */ |
| 33 | struct smm_relocation_attrs { |
| 34 | uint32_t smbase; |
| 35 | uint32_t tseg_base; |
| 36 | uint32_t tseg_mask; |
| 37 | }; |
| 38 | |
| 39 | static struct smm_relocation_attrs relo_attrs; |
| 40 | |
| 41 | /* |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 42 | * Do essential initialization tasks before APs can be fired up - |
| 43 | * |
| 44 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 45 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 46 | * apply the incomplete solution as the BSP is calculating it. |
| 47 | */ |
| 48 | static void pre_mp_init(void) |
| 49 | { |
| 50 | x86_setup_mtrrs_with_detect(); |
Marshall Dawson | 0814b12 | 2018-01-10 11:35:24 -0700 | [diff] [blame] | 51 | |
| 52 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 53 | mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
| 54 | |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 55 | x86_mtrr_check(); |
| 56 | } |
| 57 | |
| 58 | static int get_cpu_count(void) |
| 59 | { |
| 60 | device_t nb = dev_find_slot(0, HT_DEVFN); |
| 61 | return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; |
| 62 | } |
| 63 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 64 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 65 | size_t *smm_save_state_size) |
| 66 | { |
| 67 | void *smm_base; |
| 68 | size_t smm_size; |
| 69 | void *handler_base; |
| 70 | size_t handler_size; |
| 71 | |
| 72 | /* Initialize global tracking state. */ |
| 73 | smm_region_info(&smm_base, &smm_size); |
| 74 | smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); |
| 75 | |
| 76 | relo_attrs.smbase = (uint32_t)smm_base; |
| 77 | relo_attrs.tseg_base = relo_attrs.smbase; |
| 78 | relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB); |
Marshall Dawson | 2a5e15c | 2018-01-24 12:07:11 -0700 | [diff] [blame] | 79 | relo_attrs.tseg_mask |= SMM_TSEG_WB; |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 80 | |
| 81 | *perm_smbase = (uintptr_t)handler_base; |
| 82 | *perm_smsize = handler_size; |
| 83 | *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); |
| 84 | } |
| 85 | |
| 86 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 87 | uintptr_t staggered_smbase) |
| 88 | { |
| 89 | msr_t tseg_base, tseg_mask; |
| 90 | amd64_smm_state_save_area_t *smm_state; |
| 91 | |
| 92 | tseg_base.lo = relo_attrs.tseg_base; |
| 93 | tseg_base.hi = 0; |
| 94 | wrmsr(MSR_TSEG_BASE, tseg_base); |
| 95 | tseg_mask.lo = relo_attrs.tseg_mask; |
| 96 | tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1); |
| 97 | wrmsr(MSR_SMM_MASK, tseg_mask); |
| 98 | smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); |
| 99 | smm_state->smbase = staggered_smbase; |
| 100 | } |
| 101 | |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 102 | static const struct mp_ops mp_ops = { |
| 103 | .pre_mp_init = pre_mp_init, |
| 104 | .get_cpu_count = get_cpu_count, |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 105 | .get_smm_info = get_smm_info, |
| 106 | .relocation_handler = relocation_handler, |
| 107 | .post_mp_init = enable_smi_generation, |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | void stoney_init_cpus(struct device *dev) |
| 111 | { |
| 112 | /* Clear for take-off */ |
| 113 | if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) |
| 114 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 115 | } |