amd/stoneyridge: Move TValid and SmmLock to end of POST
Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 86429e2..5042cbc 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -76,7 +76,7 @@
relo_attrs.smbase = (uint32_t)smm_base;
relo_attrs.tseg_base = relo_attrs.smbase;
relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
- relo_attrs.tseg_mask |= SMM_TSEG_WB | SMM_TSEG_VALID;
+ relo_attrs.tseg_mask |= SMM_TSEG_WB;
*perm_smbase = (uintptr_t)handler_base;
*perm_smsize = handler_size;