| Fabian Kunkel | 171e2c9 | 2016-07-27 17:30:49 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <device/pci_def.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <arch/acpi.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/stages.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <arch/cpu.h> |
| 25 | #include <cpu/x86/lapic.h> |
| 26 | #include <console/console.h> |
| 27 | #include <commonlib/loglevel.h> |
| 28 | #include <cpu/amd/car.h> |
| 29 | #include <northbridge/amd/pi/agesawrapper.h> |
| 30 | #include <northbridge/amd/pi/agesawrapper_call.h> |
| 31 | #include <cpu/x86/bist.h> |
| 32 | #include <cpu/x86/lapic.h> |
| 33 | #include <southbridge/amd/pi/hudson/hudson.h> |
| 34 | #include <cpu/amd/pi/s3_resume.h> |
| 35 | |
| 36 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 37 | { |
| 38 | u32 val; |
| 39 | |
| 40 | /* |
| 41 | * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for |
| 42 | * LpcClk[1:0]". This following register setting has been |
| 43 | * replicated in every reference design since Parmer, so it is |
| 44 | * believed to be required even though it is not documented in |
| 45 | * the SoC BKDGs. Without this setting, there is no serial |
| 46 | * output. |
| 47 | */ |
| 48 | outb(0xD2, 0xcd6); |
| 49 | outb(0x00, 0xcd7); |
| 50 | |
| 51 | amd_initmmio(); |
| 52 | |
| 53 | hudson_lpc_port80(); |
| 54 | |
| 55 | if (!cpu_init_detectedx && boot_cpu()) { |
| 56 | post_code(0x30); |
| 57 | |
| 58 | post_code(0x31); |
| 59 | console_init(); |
| 60 | } |
| 61 | |
| 62 | /* Halt if there was a built in self test failure */ |
| 63 | post_code(0x34); |
| 64 | report_bist_failure(bist); |
| 65 | |
| 66 | /* Load MPB */ |
| 67 | val = cpuid_eax(1); |
| 68 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
| 69 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
| 70 | |
| 71 | /* |
| 72 | * This refers to LpcClkDrvSth settling time. Without this setting, processor |
| 73 | * initialization is slow or incorrect, so this wait has been replicated from |
| 74 | * earlier development boards. |
| 75 | */ |
| 76 | { |
| 77 | int i; |
| 78 | for(i = 0; i < 200000; i++) inb(0xCD6); |
| 79 | } |
| 80 | |
| 81 | post_code(0x37); |
| 82 | AGESAWRAPPER(amdinitreset); |
| 83 | |
| 84 | post_code(0x38); |
| 85 | printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); |
| 86 | |
| 87 | post_code(0x39); |
| 88 | AGESAWRAPPER(amdinitearly); |
| 89 | int s3resume = acpi_is_wakeup_s3(); |
| 90 | if (!s3resume) { |
| 91 | post_code(0x40); |
| 92 | AGESAWRAPPER(amdinitpost); |
| 93 | |
| 94 | //PspMboxBiosCmdDramInfo(); |
| 95 | post_code(0x41); |
| 96 | AGESAWRAPPER(amdinitenv); |
| 97 | /* |
| 98 | If code hangs here, please check cahaltasm.S |
| 99 | */ |
| 100 | disable_cache_as_ram(); |
| 101 | } else { /* S3 detect */ |
| 102 | printk(BIOS_INFO, "S3 detected\n"); |
| 103 | |
| 104 | post_code(0x60); |
| 105 | AGESAWRAPPER(amdinitresume); |
| 106 | |
| 107 | AGESAWRAPPER(amds3laterestore); |
| 108 | |
| 109 | post_code(0x61); |
| 110 | prepare_for_resume(); |
| 111 | } |
| 112 | |
| 113 | outb(0xEA, 0xCD6); |
| 114 | outb(0x1, 0xcd7); |
| 115 | |
| 116 | post_code(0x50); |
| 117 | copy_and_run(); |
| 118 | |
| 119 | post_code(0x54); /* Should never see this post code. */ |
| 120 | } |