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review.coreboot.org / coreboot / 77c226ac9bad0ac53fd8d1b81dd38a5c4c924e52 / . / src / soc / intel / xeon_sp / skx / Kconfig
blob: 18e5f2f59a8c88a6fe3ade438c3aac529a4f2b1b [file] [log] [blame]
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]1## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]2
3if SOC_INTEL_SKYLAKE_SP
4
5config MAINBOARD_USES_FSP2_0
6 bool
7 default y
8
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]9config FSP_HEADER_PATH
10 string "Location of FSP headers"
11 depends on MAINBOARD_USES_FSP2_0
12 default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
13
14config MAX_SOCKET
15 int
16 default 2
17
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]18# For 2S config, the number of cpus could be as high as
19# 2 threads * 20 cores * 2 sockets
20config MAX_CPUS
21 int
22 default 80
23
24config PCR_BASE_ADDRESS
25 hex
26 default 0xfd000000
27 help
28 This option allows you to select MMIO Base Address of sideband bus.
29
30config DCACHE_RAM_BASE
31 hex
32 default 0xfe800000
33
34config DCACHE_RAM_SIZE
35 hex
36 default 0x200000
37
38config DCACHE_BSP_STACK_SIZE
39 hex
40 default 0x10000
41
42config CPU_MICROCODE_CBFS_LOC
43 hex
44 default 0xfff0fdc0
45
46config CPU_MICROCODE_CBFS_LEN
47 hex
48 default 0x7C00
49
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]50config HEAP_SIZE
51 hex
52 default 0x80000
53
Rocky Phagura17a798b2020-10-08 13:32:41 -0700[diff] [blame]54config IED_REGION_SIZE
55 hex
56 default 0x400000
57
Johnny Linc05aa262021-06-22 11:35:41 +0800[diff] [blame]58config IFD_CHIPSET
59 string
60 default "lbg"
61
Christian Walter106def92022-06-29 18:23:51 +0200[diff] [blame]62config XEON_SP_HAVE_IIO_IOAPIC
63 bool
64 default y
65
Andrey Petrov662da6c2020-03-16 22:46:57 -0700[diff] [blame]66endif