blob: 071ff7f0ff3141ec06ad79929b8ae1bc9738f433 [file] [log] [blame]
Patrick Rudolphf1a4ae02019-09-30 11:02:04 +02001/*
Patrick Rudolphf1a4ae02019-09-30 11:02:04 +02002 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the
4 * "Software"), to deal in the Software without restriction, including
5 * without limitation the rights to use, copy, modify, merge, publish,
6 * distribute, sub license, and/or sell copies of the Software, and to
7 * permit persons to whom the Software is furnished to do so, subject to
8 * the following conditions:
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
11 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
12 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
13 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
15 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
16 * USE OR OTHER DEALINGS IN THE SOFTWARE.
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 */
23
Patrick Georgi16849bb2020-05-10 17:52:40 +020024/*
25 * Copied from Linux drivers/gpu/drm/ast/ast_mode.c
26 */
Patrick Rudolphf1a4ae02019-09-30 11:02:04 +020027#include <edid.h>
28
29#include "ast_drv.h"
30
31/*
32 * Set framebuffer MMIO address, which must fall into BAR0 MMIO window.
33 *
34 * Complete reimplementation as the original expects multiple kernel internal
35 * subsystems to be present.
36 */
37int ast_crtc_do_set_base(struct drm_crtc *crtc)
38{
39 struct ast_private *ast = crtc->dev->dev_private;
40 struct drm_framebuffer *fb = crtc->primary->fb;
41
42 /* PCI BAR 0 */
43 struct resource *res = find_resource(crtc->dev->pdev, 0x10);
44 if (!res) {
45 printk(BIOS_ERR, "BAR0 resource not found.\n");
46 return -EIO;
47 }
48
49 if (res->size < fb->pitches[0] * crtc->mode.vdisplay) {
50 dev_err(dev->pdev, "Framebuffer doesn't fit into BAR0 MMIO window\n");
51 return -ENOMEM;
52 }
53
54 fb->mmio_addr = (u32)res2mmio(res, 4095, 4095);
55
56 ast_set_offset_reg(crtc);
57 ast_set_start_address_crt1(ast, fb->mmio_addr);
58
59 return 0;
60}
61
62static void ast_edid_to_drmmode(struct edid *edid, struct drm_display_mode *mode)
63{
64 memset(mode, 0, sizeof(*mode));
65
66 mode->hdisplay = edid->mode.ha;
67 mode->vdisplay = edid->mode.va;
68 mode->crtc_hdisplay = edid->mode.ha;
69 mode->crtc_vdisplay = edid->mode.va;
70
71 /* EDID clock is in 10kHz, but drm clock is in KHz */
72 mode->clock = edid->mode.pixel_clock * 10;
73 mode->vrefresh = edid->mode.refresh;
74
75 mode->crtc_hblank_start = edid->mode.ha;
76 mode->crtc_hblank_end = edid->mode.ha + edid->mode.hbl;
77 mode->crtc_hsync_start = edid->mode.ha + edid->mode.hso;
78 mode->crtc_hsync_end = edid->mode.ha + edid->mode.hso + edid->mode.hspw;
79 mode->crtc_htotal = mode->crtc_hblank_end;
80
81 mode->crtc_vblank_start = edid->mode.va;
82 mode->crtc_vblank_end = edid->mode.va + edid->mode.vbl;
83 mode->crtc_vsync_start = edid->mode.va + edid->mode.vso;
84 mode->crtc_vsync_end = edid->mode.va + edid->mode.vso + edid->mode.vspw;
85 mode->crtc_vtotal = mode->crtc_vblank_end;
86
87 mode->flags = 0;
88 if (edid->mode.phsync == '+')
89 mode->flags |= DRM_MODE_FLAG_PHSYNC;
90 else
91 mode->flags |= DRM_MODE_FLAG_NHSYNC;
92
93 if (edid->mode.pvsync == '+')
94 mode->flags |= DRM_MODE_FLAG_PVSYNC;
95 else
96 mode->flags |= DRM_MODE_FLAG_NVSYNC;
97}
98
99static int ast_select_mode(struct drm_connector *connector,
100 struct edid *edid)
101{
102 struct ast_private *ast = connector->dev->dev_private;
103 bool widescreen;
104 u8 raw[128];
105 bool flags = false;
106
107 if (ast->tx_chip_type == AST_TX_DP501) {
108 ast->dp501_maxclk = 0xff;
109 flags = ast_dp501_read_edid(connector->dev, (u8 *)raw);
110 if (flags)
111 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
112 else
113 dev_err(dev->pdev, "I2C transmission error\n");
114 }
115
116 if (!flags)
117 ast_software_i2c_read(ast, raw);
118
119 if (decode_edid(raw, sizeof(raw), edid) != EDID_CONFORMANT) {
120 dev_err(dev->pdev, "Failed to decode EDID\n");
121 printk(BIOS_DEBUG, "Assuming VGA for KVM\n");
122
123 memset(edid, 0, sizeof(*edid));
124
125 edid->mode.pixel_clock = 6411;
126 edid->mode.refresh = 60;
127 edid->mode.ha = 1024;
128 edid->mode.hspw = 4;
129 edid->mode.hso = 56;
130 edid->mode.hbl = 264;
131 edid->mode.phsync = '-';
132
133 edid->mode.va = 768;
134 edid->mode.vspw = 3;
135 edid->mode.vso = 1;
136 edid->mode.vbl = 26;
137 edid->mode.pvsync = '+';
138 }
139
140 printk(BIOS_DEBUG, "AST: Display has %dpx x %dpx\n", edid->mode.ha, edid->mode.va);
141
142 widescreen = !!(((edid->mode.ha * 4) % (edid->mode.va * 3)));
143
144 while (ast_mode_valid(connector, edid->mode.ha, edid->mode.va) != MODE_OK) {
145 /* Select a compatible smaller mode */
146 if (edid->mode.ha > 1920 && widescreen) {
147 edid->mode.ha = 1920;
148 edid->mode.va = 1080;
149 } else if (edid->mode.ha >= 1920 && widescreen) {
150 edid->mode.ha = 1680;
151 edid->mode.va = 1050;
152 } else if (edid->mode.ha >= 1680 && widescreen) {
153 edid->mode.ha = 1600;
154 edid->mode.va = 900;
155 } else if (edid->mode.ha >= 1680 && !widescreen) {
156 edid->mode.ha = 1600;
157 edid->mode.va = 1200;
158 } else if (edid->mode.ha >= 1600 && widescreen) {
159 edid->mode.ha = 1440;
160 edid->mode.va = 900;
161 } else if (edid->mode.ha >= 1440 && widescreen) {
162 edid->mode.ha = 1360;
163 edid->mode.va = 768;
164 } else if (edid->mode.ha >= 1360 && widescreen) {
165 edid->mode.ha = 1280;
166 edid->mode.va = 800;
167 } else if (edid->mode.ha >= 1360 && !widescreen) {
168 edid->mode.ha = 1280;
169 edid->mode.va = 1024;
170 } else if (edid->mode.ha >= 1280) {
171 edid->mode.ha = 1024;
172 edid->mode.va = 768;
173 } else if (edid->mode.ha >= 1024) {
174 edid->mode.ha = 800;
175 edid->mode.va = 600;
176 } else if (edid->mode.ha >= 800) {
177 edid->mode.ha = 640;
178 edid->mode.va = 480;
179 } else {
180 dev_err(dev->pdev, "No compatible mode found.\n");
181
182 return -EIO;
183 }
184 };
185
186 return 0;
187}
188
189int ast_driver_framebuffer_init(struct drm_device *dev, int flags)
190{
191 struct drm_display_mode adjusted_mode;
192 struct drm_crtc crtc;
193 struct drm_format format;
194 struct drm_primary primary;
195 struct drm_framebuffer fb;
196 struct drm_connector connector;
197 struct edid edid;
198 int ret;
199
200 /* Init wrapper structs */
201 connector.dev = dev;
202
203 format.cpp[0] = 4; /* 32 BPP */
204 fb.format = &format;
205
206 primary.fb = &fb;
207
208 crtc.dev = dev;
209 crtc.primary = &primary;
210
211 /* Read EDID and find mode */
212 ret = ast_select_mode(&connector, &edid);
213 if (ret) {
214 dev_err(dev->pdev, "Failed to select mode.\n");
215 return ret;
216 }
217
218 /* Updated edid for set_vbe_mode_info_valid */
219 edid.x_resolution = edid.mode.ha;
220 edid.y_resolution = edid.mode.va;
221 edid.framebuffer_bits_per_pixel = format.cpp[0] * 8;
222 edid.bytes_per_line = ALIGN_UP(edid.x_resolution * format.cpp[0], 8);
223
224 /* Updated framebuffer info for ast_crtc_mode_set */
225 fb.pitches[0] = edid.bytes_per_line;
226
227 printk(BIOS_DEBUG, "Using framebuffer %dpx x %dpx pitch %d @ %d BPP\n",
228 edid.x_resolution, edid.y_resolution, edid.bytes_per_line,
229 edid.framebuffer_bits_per_pixel);
230
231 /* Convert EDID to AST DRM mode */
232 ast_edid_to_drmmode(&edid, &crtc.mode);
233
234 memcpy(&adjusted_mode, &crtc.mode, sizeof(crtc.mode));
235
236 ret = ast_crtc_mode_set(&crtc, &crtc.mode, &adjusted_mode);
237 if (ret) {
238 dev_err(dev->pdev, "Failed to set mode.\n");
239 return ret;
240 }
241
242 ast_hide_cursor(&crtc);
243
244 /* Advertise new mode */
245 set_vbe_mode_info_valid(&edid, fb.mmio_addr);
246
247 /* Clear display */
248 memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution);
249
250 return 0;
251}