Angel Pons | 6ad9176 | 2020-04-03 01:23:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 2 | |
| 3 | #include <bootstate.h> |
Mario Scheithauer | 7ad8b09 | 2023-05-09 09:49:13 +0200 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <gpio.h> |
| 9 | #include <hwilib.h> |
| 10 | #include <intelblocks/lpc_lib.h> |
| 11 | #include <intelblocks/pcr.h> |
| 12 | #include <soc/pcr_ids.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 13 | #include <baseboard/variants.h> |
Elyes HAOUAS | e39db68 | 2019-05-15 21:12:31 +0200 | [diff] [blame] | 14 | #include <types.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 15 | |
Mario Scheithauer | 15e1d97 | 2023-06-28 10:18:29 +0200 | [diff] [blame^] | 16 | #define TX_DWORD3_P0 0xc8c |
| 17 | #define TX_SWING_MASK 0x00ff0000 |
| 18 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 19 | void variant_mainboard_final(void) |
| 20 | { |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 21 | struct device *dev = NULL; |
| 22 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 23 | /* PIR6 register mapping for PCIe root ports |
| 24 | INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# */ |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 25 | pcr_write16(PID_ITSS, 0x314c, 0x0321); |
| 26 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 27 | /* Enable CLKRUN_EN for power gating LPC */ |
| 28 | lpc_enable_pci_clk_cntl(); |
| 29 | |
| 30 | /* |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 31 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D |
| 32 | * bit3 and bit0. |
| 33 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit |
| 34 | * [3:0]. |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 35 | */ |
| 36 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
| 37 | |
Mario Scheithauer | 15e1d97 | 2023-06-28 10:18:29 +0200 | [diff] [blame^] | 38 | /* |
| 39 | * Correct the SATA transmit signal via the High Speed I/O Transmit |
| 40 | * Control Register 3 on SATA port 0. |
| 41 | * Bit [23:16] sets the output voltage swing for TX line. |
| 42 | * The value 0x5a sets the swing level to 0.7 V. |
| 43 | */ |
| 44 | pcr_rmw32(PID_MODPHY, TX_DWORD3_P0, ~TX_SWING_MASK, 0x5a << 16); |
| 45 | |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 46 | /* Set Master Enable for on-board PCI device if allowed. */ |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 47 | dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0); |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 48 | if (dev) { |
Werner Zeh | e8fc8f3 | 2021-07-22 06:44:01 +0200 | [diff] [blame] | 49 | if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) |
Werner Zeh | 1412ffa | 2021-07-20 07:33:20 +0200 | [diff] [blame] | 50 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 51 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 52 | /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI |
| 53 | Bridge. */ |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 54 | struct device *parent = dev->bus->dev; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 55 | if (parent && parent->device == PCI_DID_TI_XIO2001) |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 56 | pci_write_config8(parent, 0xd8, 0x0f); |
| 57 | } |
| 58 | |
Mario Scheithauer | 08706a3 | 2023-05-09 13:34:05 +0200 | [diff] [blame] | 59 | /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this |
| 60 | mainboard. */ |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 61 | dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0); |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 62 | if (dev) { |
| 63 | struct device *parent = dev->bus->dev; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 64 | if (parent && parent->device == PCI_DID_TI_XIO2001) |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 65 | pci_write_config8(parent, 0xd8, 0x3e); |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 66 | } |
Mario Scheithauer | 7ad8b09 | 2023-05-09 09:49:13 +0200 | [diff] [blame] | 67 | |
| 68 | /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 |
| 69 | and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is |
| 70 | then used on the mainboard to generate the right reset timing. */ |
| 71 | outb(FULL_RST, RST_CNT); |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 72 | } |
| 73 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 74 | static void finalize_boot(void *unused) |
| 75 | { |
| 76 | /* Set coreboot ready LED. */ |
| 77 | gpio_output(CNV_RGI_DT, 1); |
| 78 | } |
| 79 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 80 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |