mb/siemens/mc_apl: Correct multi-line comment style for all Siemens APL Boards
Change-Id: I6578aee52e6900b25441dc119383856acc480231
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
index 82b8c5b..d01d547 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
@@ -18,29 +18,24 @@
{
struct device *dev = NULL;
- /*
- * PIR6 register mapping for PCIe root ports
- * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
- */
+ /* PIR6 register mapping for PCIe root ports
+ INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# */
pcr_write16(PID_ITSS, 0x314c, 0x0321);
/* Enable CLKRUN_EN for power gating LPC */
lpc_enable_pci_clk_cntl();
/*
- * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
- * offset 0x341D bit3 and bit0.
- * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
- * offset 0x341C bit [3:0].
+ * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D
+ * bit3 and bit0.
+ * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit
+ * [3:0].
*/
pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
- /*
- * Correct the SATA transmit signal via the High Speed I/O Transmit
- * Control Register 3.
- * Bit [23:16] set the output voltage swing for TX line.
- * The value 0x4a sets the swing level to 0.58 V.
- */
+ /* Correct the SATA transmit signal via the High Speed I/O Transmit Control Register 3.
+ Bit [23:16] set the output voltage swing for TX line. The value 0x4a sets the swing
+ level to 0.58 V. */
pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
/* Set Master Enable for on-board PCI device if allowed. */
@@ -49,16 +44,15 @@
if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
- /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe
- * to PCI Bridge. */
+ /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI
+ Bridge. */
struct device *parent = dev->bus->dev;
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x0f);
}
- /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI
- * Bridge on this mainboard.
- */
+ /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this
+ mainboard. */
dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
if (dev) {
struct device *parent = dev->bus->dev;