Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 4 | * Copyright (C) 2014 Vladimir Serbinenko |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 18 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 20 | #include <device/pci_def.h> |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 21 | #include <northbridge/intel/sandybridge/sandybridge.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 22 | #include "pch.h" |
| 23 | |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 24 | void early_usb_init(const struct southbridge_usb_port *portmap) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 25 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 26 | u32 reg32; |
| 27 | const u32 rcba_dump[8] = { |
| 28 | /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, |
| 29 | /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, |
| 30 | }; |
Vagiz Trakhanov | 216ad21 | 2017-09-28 14:54:52 +0000 | [diff] [blame] | 31 | const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, |
| 32 | 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, |
| 33 | 0x20000353 }; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 34 | int i; |
| 35 | /* Activate PMBAR. */ |
| 36 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 37 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 38 | /* Enable ACPI BAR */ |
| 39 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 40 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 41 | /* Unlock registers. */ |
Patrick Rudolph | 87b5ff0 | 2017-05-28 13:57:04 +0200 | [diff] [blame] | 42 | outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, |
| 43 | DEFAULT_PMBASE | UPRWC); |
| 44 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 45 | for (i = 0; i < 14; i++) |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 46 | write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 47 | currents[portmap[i].current]); |
| 48 | for (i = 0; i < 10; i++) |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 49 | write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 50 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 51 | for (i = 0; i < 8; i++) |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 52 | write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 53 | for (i = 0; i < 8; i++) |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 54 | write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 55 | reg32 = 0; |
| 56 | for (i = 0; i < 14; i++) |
| 57 | if (!portmap[i].enabled) |
| 58 | reg32 |= (1 << i); |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 59 | write32(DEFAULT_RCBABASE + USBPDO, reg32); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 60 | reg32 = 0; |
| 61 | for (i = 0; i < 8; i++) |
| 62 | if (portmap[i].enabled && portmap[i].oc_pin >= 0) |
| 63 | reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 64 | write32(DEFAULT_RCBABASE + USBOCM1, reg32); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 65 | reg32 = 0; |
| 66 | for (i = 8; i < 14; i++) |
| 67 | if (portmap[i].enabled && portmap[i].oc_pin >= 4) |
| 68 | reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 69 | write32(DEFAULT_RCBABASE + USBOCM2, reg32); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 70 | for (i = 0; i < 22; i++) |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 71 | write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 72 | |
Elyes HAOUAS | f385e9d | 2018-11-01 19:13:08 +0100 | [diff] [blame] | 73 | pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 74 | |
| 75 | /* Relock registers. */ |
Patrick Rudolph | 87b5ff0 | 2017-05-28 13:57:04 +0200 | [diff] [blame] | 76 | outw(0, DEFAULT_PMBASE | UPRWC); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 77 | } |