Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <delay.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 24 | #include <soc/iobp.h> |
| 25 | #include <soc/ramstage.h> |
| 26 | #include <soc/rcba.h> |
| 27 | #include <soc/sata.h> |
| 28 | #include <soc/intel/broadwell/chip.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | |
| 30 | static inline u32 sir_read(struct device *dev, int idx) |
| 31 | { |
| 32 | pci_write_config32(dev, SATA_SIRI, idx); |
| 33 | return pci_read_config32(dev, SATA_SIRD); |
| 34 | } |
| 35 | |
| 36 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 37 | { |
| 38 | pci_write_config32(dev, SATA_SIRI, idx); |
| 39 | pci_write_config32(dev, SATA_SIRD, value); |
| 40 | } |
| 41 | |
| 42 | static void sata_init(struct device *dev) |
| 43 | { |
| 44 | config_t *config = dev->chip_info; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 45 | u32 reg32; |
| 46 | u8 *abar; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 47 | u16 reg16; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 48 | int port; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 49 | |
| 50 | printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); |
| 51 | |
| 52 | /* Enable BARs */ |
| 53 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 54 | |
| 55 | /* Set Interrupt Line */ |
| 56 | /* Interrupt Pin is set by D31IP.PIP */ |
| 57 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); |
| 58 | |
| 59 | /* Set timings */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 60 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); |
| 61 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 62 | |
| 63 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 64 | reg16 = pci_read_config16(dev, 0x92); |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 65 | reg16 &= ~0xf; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 66 | reg16 |= 0x8000 | config->sata_port_map; |
| 67 | pci_write_config16(dev, 0x92, reg16); |
| 68 | udelay(2); |
| 69 | |
| 70 | /* Setup register 98h */ |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 71 | reg32 = pci_read_config32(dev, 0x98); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 72 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 73 | reg32 |= 1 << 23; |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 74 | reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 75 | pci_write_config32(dev, 0x98, reg32); |
| 76 | |
| 77 | /* Setup register 9Ch */ |
| 78 | reg16 = 0; /* Disable alternate ID */ |
| 79 | reg16 = 1 << 5; /* BWG step 12 */ |
| 80 | pci_write_config16(dev, 0x9c, reg16); |
| 81 | |
| 82 | /* SATA Initialization register */ |
| 83 | reg32 = 0x183; |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 84 | reg32 |= (config->sata_port_map ^ 0xf) << 24; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 85 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 86 | pci_write_config32(dev, 0x94, reg32); |
| 87 | |
| 88 | /* Initialize AHCI memory-mapped space */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 89 | abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); |
| 90 | printk(BIOS_DEBUG, "ABAR: %p\n", abar); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 91 | |
Duncan Laurie | 55228ba | 2014-08-25 10:14:08 -0700 | [diff] [blame] | 92 | /* CAP (HBA Capabilities) : enable power management */ |
| 93 | reg32 = read32(abar + 0x00); |
| 94 | reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ |
| 95 | reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ |
| 96 | reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ |
| 97 | write32(abar + 0x00, reg32); |
| 98 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 99 | /* PI (Ports implemented) */ |
| 100 | write32(abar + 0x0c, config->sata_port_map); |
| 101 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 102 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 103 | |
| 104 | /* CAP2 (HBA Capabilities Extended)*/ |
Duncan Laurie | 1b0d5a3 | 2014-08-13 16:59:34 -0700 | [diff] [blame] | 105 | if (config->sata_devslp_disable) { |
| 106 | reg32 = read32(abar + 0x24); |
| 107 | reg32 &= ~(1 << 3); |
| 108 | write32(abar + 0x24, reg32); |
| 109 | } else { |
| 110 | /* Enable DEVSLP */ |
| 111 | reg32 = read32(abar + 0x24); |
| 112 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 113 | write32(abar + 0x24, reg32); |
| 114 | |
| 115 | for (port = 0; port < 4; port++) { |
| 116 | if (!(config->sata_port_map & (1 << port))) |
| 117 | continue; |
| 118 | reg32 = read32(abar + 0x144 + (0x80 * port)); |
| 119 | reg32 |= (1 << 1); /* DEVSLP DSP */ |
| 120 | write32(abar + 0x144 + (0x80 * port), reg32); |
| 121 | } |
| 122 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 123 | |
| 124 | /* |
| 125 | * Static Power Gating for unused ports |
| 126 | */ |
| 127 | reg32 = RCBA32(0x3a84); |
| 128 | /* Port 3 and 2 disabled */ |
| 129 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 130 | reg32 |= (1 << 24) | (1 << 26); |
| 131 | /* Port 1 and 0 disabled */ |
| 132 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 133 | reg32 |= (1 << 20) | (1 << 18); |
| 134 | RCBA32(0x3a84) = reg32; |
| 135 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 136 | /* Set Gen3 Transmitter settings if needed */ |
| 137 | if (config->sata_port0_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 138 | pch_iobp_update(SATA_IOBP_SP0_SECRT88, |
| 139 | ~(SATA_SECRT88_VADJ_MASK << |
| 140 | SATA_SECRT88_VADJ_SHIFT), |
| 141 | (config->sata_port0_gen3_tx & |
| 142 | SATA_SECRT88_VADJ_MASK) |
| 143 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 144 | |
| 145 | if (config->sata_port1_gen3_tx) |
Duncan Laurie | b63d341 | 2015-01-06 13:32:42 -0800 | [diff] [blame] | 146 | pch_iobp_update(SATA_IOBP_SP1_SECRT88, |
| 147 | ~(SATA_SECRT88_VADJ_MASK << |
| 148 | SATA_SECRT88_VADJ_SHIFT), |
| 149 | (config->sata_port1_gen3_tx & |
| 150 | SATA_SECRT88_VADJ_MASK) |
| 151 | << SATA_SECRT88_VADJ_SHIFT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 152 | |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 153 | if (config->sata_port2_gen3_tx) |
| 154 | pch_iobp_update(SATA_IOBP_SP2_SECRT88, |
| 155 | ~(SATA_SECRT88_VADJ_MASK << |
| 156 | SATA_SECRT88_VADJ_SHIFT), |
| 157 | (config->sata_port2_gen3_tx & |
| 158 | SATA_SECRT88_VADJ_MASK) |
| 159 | << SATA_SECRT88_VADJ_SHIFT); |
| 160 | |
| 161 | if (config->sata_port3_gen3_tx) |
| 162 | pch_iobp_update(SATA_IOBP_SP3_SECRT88, |
| 163 | ~(SATA_SECRT88_VADJ_MASK << |
| 164 | SATA_SECRT88_VADJ_SHIFT), |
Youness Alaoui | 601aa31 | 2017-02-27 12:03:39 -0500 | [diff] [blame] | 165 | (config->sata_port3_gen3_tx & |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 166 | SATA_SECRT88_VADJ_MASK) |
| 167 | << SATA_SECRT88_VADJ_SHIFT); |
| 168 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 169 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 170 | if (config->sata_port0_gen3_dtle) { |
| 171 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 172 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 173 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 174 | << SATA_DTLE_DATA_SHIFT); |
| 175 | |
| 176 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 177 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 178 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 179 | << SATA_DTLE_EDGE_SHIFT); |
| 180 | } |
| 181 | |
| 182 | if (config->sata_port1_gen3_dtle) { |
| 183 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 184 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 185 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 186 | << SATA_DTLE_DATA_SHIFT); |
| 187 | |
| 188 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 189 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 190 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 191 | << SATA_DTLE_EDGE_SHIFT); |
| 192 | } |
| 193 | |
Youness Alaoui | 696ebc2 | 2017-02-07 13:54:45 -0500 | [diff] [blame] | 194 | if (config->sata_port2_gen3_dtle) { |
| 195 | pch_iobp_update(SATA_IOBP_SP2DTLE_DATA, |
| 196 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 197 | (config->sata_port2_gen3_dtle & SATA_DTLE_MASK) |
| 198 | << SATA_DTLE_DATA_SHIFT); |
| 199 | |
| 200 | pch_iobp_update(SATA_IOBP_SP2DTLE_EDGE, |
| 201 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 202 | (config->sata_port2_gen3_dtle & SATA_DTLE_MASK) |
| 203 | << SATA_DTLE_EDGE_SHIFT); |
| 204 | } |
| 205 | if (config->sata_port3_gen3_dtle) { |
| 206 | pch_iobp_update(SATA_IOBP_SP3DTLE_DATA, |
| 207 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 208 | (config->sata_port3_gen3_dtle & SATA_DTLE_MASK) |
| 209 | << SATA_DTLE_DATA_SHIFT); |
| 210 | |
| 211 | pch_iobp_update(SATA_IOBP_SP3DTLE_EDGE, |
| 212 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 213 | (config->sata_port3_gen3_dtle & SATA_DTLE_MASK) |
| 214 | << SATA_DTLE_EDGE_SHIFT); |
| 215 | } |
| 216 | |
| 217 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 218 | /* |
| 219 | * Additional Programming Requirements for Power Optimizer |
| 220 | */ |
| 221 | |
| 222 | /* Step 1 */ |
| 223 | sir_write(dev, 0x64, 0x883c9003); |
| 224 | |
| 225 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
| 226 | reg32 = sir_read(dev, 0x68); |
| 227 | reg32 &= 0xffff0000; |
| 228 | reg32 |= 0x880a; |
| 229 | sir_write(dev, 0x68, reg32); |
| 230 | |
| 231 | /* Step 3: SIR 60h[3] = 1 */ |
| 232 | reg32 = sir_read(dev, 0x60); |
| 233 | reg32 |= (1 << 3); |
| 234 | sir_write(dev, 0x60, reg32); |
| 235 | |
| 236 | /* Step 4: SIR 60h[0] = 1 */ |
| 237 | reg32 = sir_read(dev, 0x60); |
| 238 | reg32 |= (1 << 0); |
| 239 | sir_write(dev, 0x60, reg32); |
| 240 | |
| 241 | /* Step 5: SIR 60h[1] = 1 */ |
| 242 | reg32 = sir_read(dev, 0x60); |
| 243 | reg32 |= (1 << 1); |
| 244 | sir_write(dev, 0x60, reg32); |
| 245 | |
| 246 | /* Clock Gating */ |
| 247 | sir_write(dev, 0x70, 0x3f00bf1f); |
| 248 | sir_write(dev, 0x54, 0xcf000f0f); |
| 249 | sir_write(dev, 0x58, 0x00190000); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 250 | RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 251 | |
| 252 | reg32 = pci_read_config32(dev, 0x300); |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 253 | reg32 |= (1 << 17) | (1 << 16) | (1 << 19); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 254 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
| 255 | pci_write_config32(dev, 0x300, reg32); |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 256 | |
Kane Chen | 4613472 | 2014-08-28 17:05:06 -0700 | [diff] [blame] | 257 | reg32 = pci_read_config32(dev, 0x98); |
| 258 | reg32 |= 1 << 29; |
| 259 | pci_write_config32(dev, 0x98, reg32); |
| 260 | |
Kane Chen | 8c1fd78 | 2014-08-19 10:51:46 -0700 | [diff] [blame] | 261 | /* Register Lock */ |
| 262 | reg32 = pci_read_config32(dev, 0x9c); |
| 263 | reg32 |= (1 << 31); |
| 264 | pci_write_config32(dev, 0x9c, reg32); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | /* |
| 268 | * Set SATA controller mode early so the resource allocator can |
| 269 | * properly assign IO/Memory resources for the controller. |
| 270 | */ |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 271 | static void sata_enable(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 272 | { |
| 273 | /* Get the chip configuration */ |
| 274 | config_t *config = dev->chip_info; |
| 275 | u16 map = 0x0060; |
| 276 | |
Wenkai Du | 038cce2 | 2014-12-05 14:04:10 -0800 | [diff] [blame] | 277 | map |= (config->sata_port_map ^ 0xf) << 8; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 278 | |
| 279 | pci_write_config16(dev, 0x90, map); |
| 280 | } |
| 281 | |
| 282 | static struct device_operations sata_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 283 | .read_resources = pci_dev_read_resources, |
| 284 | .set_resources = pci_dev_set_resources, |
| 285 | .enable_resources = pci_dev_enable_resources, |
| 286 | .init = sata_init, |
| 287 | .enable = sata_enable, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 288 | .ops_pci = &broadwell_pci_ops, |
| 289 | }; |
| 290 | |
| 291 | static const unsigned short pci_device_ids[] = { |
| 292 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* LynxPoint-LP */ |
| 293 | 0x9c83, 0x9c85, 0x282a, 0x9c87, 0x282a, 0x9c8f, /* WildcatPoint */ |
| 294 | 0 |
| 295 | }; |
| 296 | |
| 297 | static const struct pci_driver pch_sata __pci_driver = { |
| 298 | .ops = &sata_ops, |
| 299 | .vendor = PCI_VENDOR_ID_INTEL, |
| 300 | .devices = pci_device_ids, |
| 301 | }; |