broadwell: Fix some errors in selftest
1. Fixed some errors in selftest compare to reference.
2. Some WA steps for xhci in sleep trap is only for lpt.
BUG=chrome-os-partner:28234
TEST=compile ok, run selftest on auron to verify
boot to OS
BRANCH=None
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131
Original-Reviewed-on: https://chromium-review.googlesource.com/215646
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf
Reviewed-on: http://review.coreboot.org/8971
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index 0e25161..6859ffc 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -209,6 +209,10 @@
reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
pci_write_config32(dev, 0x300, reg32);
+ reg32 = pci_read_config32(dev, 0x98);
+ reg32 |= 1 << 29;
+ pci_write_config32(dev, 0x98, reg32);
+
/* Register Lock */
reg32 = pci_read_config32(dev, 0x9c);
reg32 |= (1 << 31);