Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
Dave Frodin | c7eaf77 | 2014-12-01 16:33:33 -0700 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * All Rights Reserved |
Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/amd/mtrr.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <arch/acpi.h> |
Dave Frodin | c7eaf77 | 2014-12-01 16:33:33 -0700 | [diff] [blame] | 30 | #include <southbridge/amd/agesa/hudson/pci_devs.h> |
| 31 | #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame^] | 32 | #include <southbridge/amd/common/amd_pci_util.h> |
Dave Frodin | c7eaf77 | 2014-12-01 16:33:33 -0700 | [diff] [blame] | 33 | #include <northbridge/amd/agesa/family16kb/pci_devs.h> |
Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 34 | #include <northbridge/amd/agesa/BiosCallOuts.h> |
| 35 | #include <cpu/amd/agesa/s3_resume.h> |
| 36 | #include <northbridge/amd/agesa/agesawrapper.h> |
| 37 | |
Dave Frodin | c7eaf77 | 2014-12-01 16:33:33 -0700 | [diff] [blame] | 38 | /*********************************************************** |
| 39 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 40 | * This table is responsible for physically routing the PIC and |
| 41 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 42 | * is read and written via registers 0xC00/0xC01 as an |
| 43 | * Index/Data pair. These values are chipset and mainboard |
| 44 | * dependent and should be updated accordingly. |
| 45 | * |
| 46 | * These values are used by the PCI configuration space, |
| 47 | * MP Tables. TODO: Make ACPI use these values too. |
| 48 | */ |
| 49 | const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { |
| 50 | /* INTA# - INTH# */ |
| 51 | [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 52 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 53 | [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 54 | /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ |
| 55 | [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 56 | /* IMC INT0 - 5 */ |
| 57 | [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 58 | /* USB Devs 18/19/22 INTA-C */ |
| 59 | [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, |
| 60 | /* SATA */ |
| 61 | [0x41] = 0x0F, |
| 62 | }; |
| 63 | |
| 64 | const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { |
| 65 | /* INTA# - INTH# */ |
| 66 | [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, |
| 67 | /* Misc-nil,0,1,2, INT from Serial irq */ |
| 68 | [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 69 | /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ |
| 70 | [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, |
| 71 | /* IMC INT0 - 5 */ |
| 72 | [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, |
| 73 | /* USB Devs 18/19/20/22 INTA-C */ |
| 74 | [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, |
| 75 | /* SATA */ |
| 76 | [0x41] = 0x13 |
| 77 | }; |
| 78 | |
| 79 | /* |
| 80 | * This table defines the index into the picr/intr_data |
| 81 | * tables for each device. Any enabled device and slot |
| 82 | * that uses hardware interrupts should have an entry |
| 83 | * in this table to define its index into the FCH |
| 84 | * PCI_INTR register 0xC00/0xC01. This index will define |
| 85 | * the interrupt that it should use. Putting PIRQ_A into |
| 86 | * the PIN A index for a device will tell that device to |
| 87 | * use PIC IRQ 10 if it uses PIN A for its hardware INT. |
| 88 | */ |
| 89 | static const struct pirq_struct mainboard_pirq_data[] = { |
| 90 | /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ |
| 91 | {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ |
| 92 | {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ |
| 93 | {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ |
| 94 | {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ |
| 95 | {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ |
| 96 | {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ |
| 97 | {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ |
| 98 | {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ |
| 99 | {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ |
| 100 | {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ |
| 101 | {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ |
| 102 | {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ |
| 103 | {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ |
| 104 | {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ |
| 105 | {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ |
| 106 | {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ |
| 107 | }; |
| 108 | |
| 109 | const u8 *picr_data = mainboard_picr_data; |
| 110 | const u8 *intr_data = mainboard_intr_data; |
| 111 | |
| 112 | /* PIRQ Setup */ |
| 113 | static void pirq_setup(void) |
| 114 | { |
| 115 | pirq_data_ptr = mainboard_pirq_data; |
| 116 | pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); |
| 117 | intr_data_ptr = mainboard_intr_data; |
| 118 | picr_data_ptr = mainboard_picr_data; |
| 119 | } |
| 120 | |
Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 121 | /********************************************** |
| 122 | * enable the dedicated function in mainboard. |
| 123 | **********************************************/ |
| 124 | static void mainboard_enable(device_t dev) |
| 125 | { |
| 126 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 127 | |
| 128 | if (acpi_is_wakeup_s3()) |
| 129 | agesawrapper_fchs3earlyrestore(); |
Dave Frodin | c7eaf77 | 2014-12-01 16:33:33 -0700 | [diff] [blame] | 130 | |
| 131 | /* Initialize the PIRQ data structures for consumption */ |
| 132 | pirq_setup(); |
Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | struct chip_operations mainboard_ops = { |
| 136 | .enable_dev = mainboard_enable, |
| 137 | }; |