gizmosphere/gizmo2: Add the gizmo2 IRQ routing
Change-Id: Ic00790eedd48a2b78620fea329464701cd294cbb
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7723
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
diff --git a/src/mainboard/gizmosphere/gizmo2/mainboard.c b/src/mainboard/gizmosphere/gizmo2/mainboard.c
index cf02528..c4a20c6 100644
--- a/src/mainboard/gizmosphere/gizmo2/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo2/mainboard.c
@@ -2,6 +2,8 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ * All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,10 +27,97 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
+#include <southbridge/amd/agesa/hudson/pci_devs.h>
+#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
+#include <southbridge/amd/amd_pci_util.h>
+#include <northbridge/amd/agesa/family16kb/pci_devs.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/agesawrapper.h>
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+ /* INTA# - INTH# */
+ [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
+ [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ /* USB Devs 18/19/22 INTA-C */
+ [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
+ /* SATA */
+ [0x41] = 0x0F,
+};
+
+const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+ /* INTA# - INTH# */
+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+ /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,
+ /* IMC INT0 - 5 */
+ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,
+ /* USB Devs 18/19/20/22 INTA-C */
+ [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
+ /* SATA */
+ [0x41] = 0x13
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device. Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01. This index will define
+ * the interrupt that it should use. Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
+ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
+ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
+ {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */
+ {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */
+ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
+ {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
+ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
+ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
+ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
+ {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
+ {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+};
+
+const u8 *picr_data = mainboard_picr_data;
+const u8 *intr_data = mainboard_intr_data;
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
@@ -38,6 +127,9 @@
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
}
struct chip_operations mainboard_ops = {