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Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Damien Zammit43a1f782015-08-19 15:16:59 +10002
Kyösti Mälkkide640782019-12-03 07:30:26 +02003#include <arch/bootblock.h>
Angel Ponsb8b117c2020-09-15 02:26:29 +02004#include <arch/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02005#include <device/pci_ops.h>
Angel Ponsb8b117c2020-09-15 02:26:29 +02006
Arthur Heymans7843bd52019-11-11 21:56:37 +01007#include "x4x.h"
Kyösti Mälkki197a3c62019-09-27 14:32:20 +03008
Arthur Heymans7843bd52019-11-11 21:56:37 +01009void bootblock_early_northbridge_init(void)
Damien Zammit43a1f782015-08-19 15:16:59 +100010{
Damien Zammit43a1f782015-08-19 15:16:59 +100011 /* Disable LaGrande Technology (LT) */
Angel Ponsb8b117c2020-09-15 02:26:29 +020012 read32((void *)TPM_BASE_ADDRESS);
Damien Zammit43a1f782015-08-19 15:16:59 +100013
Angel Ponsb8b117c2020-09-15 02:26:29 +020014 const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
Angel Ponsd1c590a2020-08-03 16:01:39 +020015 pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
Damien Zammit43a1f782015-08-19 15:16:59 +100016}