| Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | |
| 19 | #define D0F0_PCIEXBAR_LO 0x60 |
| 20 | #define TPMBASE 0xfed40000 |
| 21 | #define TPM32(x) *((volatile u32 *)(TPMBASE + x)) |
| 22 | |
| 23 | static void bootblock_northbridge_init(void) |
| 24 | { |
| 25 | uint32_t reg32; |
| 26 | |
| 27 | /* Disable LaGrande Technology (LT) */ |
| 28 | reg32 = TPM32(0); |
| 29 | |
| 30 | reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; |
| 31 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg32); |
| 32 | } |