Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2018 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <baseboard/gpio.h> |
| 17 | #include <baseboard/variants.h> |
| 18 | #include <commonlib/helpers.h> |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 19 | #include <compiler.h> |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' |
| 23 | * table found in EDS vol 1, but some pins aren't grouped functionally in |
| 24 | * the table so those were moved for more logical grouping. |
| 25 | */ |
| 26 | static const struct pad_config gpio_table[] = { |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 27 | /* NORTHWEST COMMUNITY GPIOS */ |
| 28 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ |
| 29 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ |
| 30 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ |
| 31 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ |
| 32 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ |
| 33 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ |
| 34 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ |
| 35 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ |
| 36 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ |
| 37 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ |
| 38 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ |
| 39 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ |
| 40 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ |
| 41 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ |
| 42 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ |
| 43 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ |
| 44 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ |
| 45 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ |
| 46 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ |
| 47 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ |
| 48 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ |
| 49 | PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ |
| 50 | PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ |
| 51 | PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ |
| 52 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ |
| 53 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ |
| 54 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ |
| 55 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ |
| 56 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ |
| 57 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ |
| 58 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ |
| 59 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ |
| 60 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ |
| 61 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ |
| 62 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ |
| 63 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ |
| 64 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ |
| 65 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ |
| 66 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ |
| 67 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA3_VNN */ |
| 68 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA4_VNN */ |
| 69 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA5_VNN */ |
| 70 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_42, 0, DEEP, DN_20K, HIZCRx1, DISPUPD), /* GP_INTD_DSI_TE1 */ |
| 71 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ |
| 72 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ |
| 73 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ |
| 74 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_46, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SDA */ |
| 75 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_47, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SCL */ |
Hannah Williams | 8dce5bc | 2018-03-31 18:23:20 -0700 | [diff] [blame] | 76 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ |
| 77 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 78 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ |
| 79 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ |
| 80 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ |
| 81 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ |
| 82 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_54, 0, DEEP, NONE, HIZCRx0, ENPD), /* LPSS_I2C2_SDA */ |
| 83 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, ENPU), /* LPSS_I2C2_SCL */ |
| 84 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ |
| 85 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 86 | PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SDA - unused */ |
| 87 | PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SCL - unused */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 88 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ |
| 89 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ |
| 90 | PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ |
Justin TerAvest | 438ca72 | 2018-04-05 14:56:23 -0600 | [diff] [blame] | 91 | PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 92 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ |
| 93 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ |
| 94 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */ |
| 95 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */ |
Justin TerAvest | 22595f6 | 2018-03-15 16:28:57 -0600 | [diff] [blame] | 96 | PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ |
| 97 | PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ |
| 98 | PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ |
| 99 | PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 100 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */ |
| 101 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */ |
| 102 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ |
| 103 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ |
| 104 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_B */ |
| 105 | PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ |
| 106 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, HIZCRx0, ENPD), /* EN_PP3300_TOUCHSCREEN */ |
| 107 | PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ |
| 108 | |
| 109 | /* NORTH COMMUNITY GPIOS */ |
| 110 | |
| 111 | /* svid - unused */ |
| 112 | PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Alert - unused */ |
| 113 | PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Data - unused */ |
| 114 | PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Clk - unused */ |
| 115 | |
| 116 | /* LPSS */ |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 117 | PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ |
| 118 | PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 119 | PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 120 | PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ |
| 121 | PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 122 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_84, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_2_CLK */ |
| 123 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_85, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_SPI_2_FS0 */ |
| 124 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_86, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* stest_CNTRL -- stest */ |
| 125 | PAD_CFG_GPIO_HI_Z(GPIO_87, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO_87_PD -- stest */ |
| 126 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_88, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* LPSS_SPI_2_RXD */ |
| 127 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_89, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* LPSS_SPI_2_TXD */ |
| 128 | |
| 129 | /* Fast SPI */ |
| 130 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* FST_SPI_CS0_B */ |
| 131 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, HIZCRx0, ENPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ |
| 132 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, ENPD),/* FST_SPI_MOSI_IO0 */ |
| 133 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, ENPD),/* FST_SPI_MISO_IO1 */ |
| 134 | PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */ |
| 135 | PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */ |
| 136 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* FST_SPI_CLK */ |
| 137 | |
| 138 | /* PMU Signals */ |
| 139 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ |
| 140 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* PMU_PWRBTN_B */ |
| 141 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ |
| 142 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ |
| 143 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ |
| 144 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ |
| 145 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, NONE, DEEP, NF1, HIZCRx0, ENPD),/* EMMC_DNX_PWR_EN_B */ |
| 146 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, HIZCRx0, ENPD),/* GPIO_105 -- TOUCHSCREEN_RST */ |
| 147 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_B */ |
| 148 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ |
| 149 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/* PMU_SUSCLK */ |
| 150 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, HIZCRx1, ENPU),/* SUS_STAT_B -- BT_DISABLE_L */ |
| 151 | |
| 152 | /* I2C5 - Audio */ |
| 153 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */ |
| 154 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */ |
| 155 | |
| 156 | /* I2C6 - Trackpad */ |
| 157 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */ |
| 158 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */ |
| 159 | |
| 160 | /* I2C7 - Touchscreen */ |
| 161 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */ |
| 162 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ |
| 163 | |
| 164 | /* PCIE_WAKE[0:3]_B */ |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 165 | PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 166 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */ |
| 167 | PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */ |
| 168 | //TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference? |
| 169 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */ |
| 170 | |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 171 | /* PCIE_CLKREQ[0:3]_B */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 172 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ |
| 173 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ |
| 174 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_122, 0, DEEP, DN_20K, HIZCRx0, ENPD),/* PCIE_CLKREQ2_B -- EN_PP3300_WLAN */ |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 175 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 176 | |
| 177 | /* DDI[0:1] SDA and SCL -- unused */ |
| 178 | PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */ |
| 179 | PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */ |
| 180 | PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */ |
| 181 | PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */ |
| 182 | |
| 183 | /* Panel 0 control */ |
| 184 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, HIZCRx0, ENPD),/* PANEL0_VDDEN*/ |
| 185 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* PANEL0_BKLTEN */ |
| 186 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* PANEL0_BKLTCTL */ |
| 187 | |
| 188 | /* Hot plug detect. */ |
| 189 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */ |
| 190 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */ |
| 191 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */ |
| 192 | |
| 193 | // TODO Need to set HIZCRx1 |
| 194 | PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */ |
Hannah Williams | e7e3567 | 2018-03-28 11:09:33 -0700 | [diff] [blame] | 195 | PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 196 | PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ |
| 197 | PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ |
| 198 | PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */ |
| 199 | PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_INT_ODL */ |
| 200 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, HIZCRx0, ENPD),/* GPIO_140 -- PEN_RESET */ |
| 201 | // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others). |
| 202 | // Settings here do not match table |
| 203 | // Also we may be able to use eSPI WAKE# Virtual Wire instead |
Shaunak Saha | 42ac977 | 2018-04-05 06:21:12 -0700 | [diff] [blame] | 204 | PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */ |
Hannah Williams | e7e3567 | 2018-03-28 11:09:33 -0700 | [diff] [blame] | 205 | PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 206 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ |
| 207 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ |
| 208 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */ |
| 209 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTCTL */ |
Shamile Khan | 12f345d | 2018-04-23 14:54:27 -0700 | [diff] [blame^] | 210 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 211 | |
| 212 | /* AUDIO COMMUNITY GPIOS*/ |
| 213 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S0_MCLK */ |
| 214 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */ |
| 215 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */ |
| 216 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */ |
| 217 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, NONE, DEEP, NF1, HIZCRx0, ENPD), /* AVS_I2S0_SDO */ |
Shamile Khan | 12f345d | 2018-04-23 14:54:27 -0700 | [diff] [blame^] | 218 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 219 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ |
| 220 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 221 | PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 222 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ |
| 223 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* AVS_I2S2_BCLK */ |
| 224 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ |
| 225 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ |
| 226 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ |
| 227 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ |
| 228 | PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ |
| 229 | PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_B1 */ |
| 230 | PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ |
| 231 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_174, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_M_CLK_AB2*/ |
| 232 | PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 */ |
| 233 | |
| 234 | /* SCC COMMUNITY GPIOS */ |
| 235 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_ALERTB */ |
| 236 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 237 | PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 238 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */ |
Shaunak Saha | cbedd8f | 2018-02-16 08:39:22 -0800 | [diff] [blame] | 239 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ |
| 240 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ |
| 241 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ |
| 242 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ |
| 243 | PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ |
| 244 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_CLK */ |
| 245 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ |
| 246 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ |
| 247 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ |
| 248 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */ |
| 249 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */ |
| 250 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */ |
| 251 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ |
| 252 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ |
| 253 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ |
| 254 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_STROBE */ |
| 255 | PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 256 | }; |
| 257 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 258 | const struct pad_config *__weak variant_gpio_table(size_t *num) |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 259 | { |
| 260 | *num = ARRAY_SIZE(gpio_table); |
| 261 | return gpio_table; |
| 262 | } |
| 263 | |
| 264 | /* GPIOs needed prior to ramstage. */ |
| 265 | static const struct pad_config early_gpio_table[] = { |
Justin TerAvest | cc6953b | 2018-03-16 13:29:42 -0600 | [diff] [blame] | 266 | PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 267 | /* GSPI0_INT */ |
Justin TerAvest | 438ca72 | 2018-04-05 14:56:23 -0600 | [diff] [blame] | 268 | PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, |
Ravi Sarawadi | c293496 | 2018-02-27 13:57:01 -0800 | [diff] [blame] | 269 | DISPUPD), /* H1_PCH_INT_ODL */ |
| 270 | /* GSPI0_CLK */ |
| 271 | PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ |
| 272 | /* GSPI0_CS# */ |
| 273 | PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ |
| 274 | /* GSPI0_MISO */ |
| 275 | PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ |
| 276 | /* GSPI0_MOSI */ |
| 277 | PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ |
Furquan Shaikh | ade3bc5 | 2018-03-28 11:53:37 -0700 | [diff] [blame] | 278 | |
| 279 | /* Enable power to wifi early in bootblock and de-assert PERST#. */ |
| 280 | PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ |
| 281 | PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ |
Furquan Shaikh | c045179 | 2018-04-27 11:34:00 -0700 | [diff] [blame] | 282 | |
| 283 | /* |
| 284 | * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak |
| 285 | * pull-up for proper operation. Since there is no external pull present |
| 286 | * on this platform, configure an internal weak pull-up. |
| 287 | */ |
| 288 | PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, |
| 289 | ENPU), /* ESPI_IO1 */ |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 290 | }; |
| 291 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 292 | const struct pad_config *__weak |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 293 | variant_early_gpio_table(size_t *num) |
| 294 | { |
| 295 | *num = ARRAY_SIZE(early_gpio_table); |
| 296 | return early_gpio_table; |
| 297 | } |
| 298 | |
| 299 | /* GPIO settings before entering sleep. */ |
| 300 | static const struct pad_config sleep_gpio_table[] = { |
| 301 | }; |
| 302 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 303 | const struct pad_config *__weak |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 304 | variant_sleep_gpio_table(size_t *num) |
| 305 | { |
| 306 | *num = ARRAY_SIZE(sleep_gpio_table); |
| 307 | return sleep_gpio_table; |
| 308 | } |
| 309 | |
| 310 | static const struct cros_gpio cros_gpios[] = { |
Hannah Williams | ecef322 | 2018-04-27 00:13:25 -0700 | [diff] [blame] | 311 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
Hannah Williams | 0a2b9d4 | 2018-04-13 21:43:05 -0700 | [diff] [blame] | 312 | CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME), |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 313 | }; |
| 314 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 315 | const struct cros_gpio *__weak variant_cros_gpios(size_t *num) |
Hannah Williams | 5e83e8b | 2018-02-09 18:35:17 -0800 | [diff] [blame] | 316 | { |
| 317 | *num = ARRAY_SIZE(cros_gpios); |
| 318 | return cros_gpios; |
| 319 | } |