blob: 55c8948063e5971180a566f89b726968a15d5e52 [file] [log] [blame]
Duncan Laurie645b3762013-02-12 14:00:47 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Duncan Laurie645b3762013-02-12 14:00:47 -080015 */
16
17#include <console/console.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
21#include "pch.h"
Kyösti Mälkkie2227a22014-02-05 13:02:55 +020022#include <device/pci_ehci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020023#include <device/pci_ops.h>
Kyösti Mälkki12b121c2019-08-18 16:33:39 +030024#include "chip.h"
Duncan Laurie645b3762013-02-12 14:00:47 -080025
26static void usb_xhci_init(struct device *dev)
27{
28 u32 reg32;
Vladimir Serbinenkob26156e2015-01-31 17:45:50 +010029 struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
Duncan Laurie645b3762013-02-12 14:00:47 -080030
31 printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
32
Nicolas Reinecke59aef5c2015-04-16 23:25:00 +020033 if (config->xhci_overcurrent_mapping)
34 pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
35
Duncan Laurie645b3762013-02-12 14:00:47 -080036 /* lock overcurrent map */
37 reg32 = pci_read_config32(dev, 0x44);
38 reg32 |= 1;
39 pci_write_config32(dev, 0x44, reg32);
40
Nicolas Reinecke0b29a7b2015-03-29 17:51:11 +020041 pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
42 pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);
Vladimir Serbinenkob26156e2015-01-31 17:45:50 +010043
Duncan Laurie645b3762013-02-12 14:00:47 -080044 /* Enable clock gating */
45 reg32 = pci_read_config32(dev, 0x40);
46 reg32 &= ~((1 << 20) | (1 << 21));
47 reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
48 reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
49 reg32 |= (1 << 31); /* lock */
50 pci_write_config32(dev, 0x40, reg32);
51
52 printk(BIOS_DEBUG, "done.\n");
53}
54
Aaron Durbinaa090cb2017-09-13 16:01:52 -060055static const char *xhci_acpi_name(const struct device *dev)
Patrick Rudolph604f6982017-06-07 09:46:52 +020056{
57 return "XHC";
58}
59
Duncan Laurie645b3762013-02-12 14:00:47 -080060static struct pci_operations xhci_pci_ops = {
Subrata Banik4a0f0712019-03-20 14:29:47 +053061 .set_subsystem = pci_dev_set_subsystem,
Duncan Laurie645b3762013-02-12 14:00:47 -080062};
63
64static struct device_operations usb_xhci_ops = {
65 .read_resources = pci_dev_read_resources,
66 .set_resources = pci_dev_set_resources,
67 .enable_resources = pci_dev_enable_resources,
68 .init = usb_xhci_init,
69 .scan_bus = 0,
70 .ops_pci = &xhci_pci_ops,
Patrick Rudolph604f6982017-06-07 09:46:52 +020071 .acpi_name = xhci_acpi_name,
Duncan Laurie645b3762013-02-12 14:00:47 -080072};
73
74static const unsigned short pci_device_ids[] = { 0x1e31, 0 };
75
76static const struct pci_driver pch_usb_xhci __pci_driver = {
77 .ops = &usb_xhci_ops,
78 .vendor = PCI_VENDOR_ID_INTEL,
79 .devices = pci_device_ids,
80};