blob: 85e450db5b6615f53eeecfcc9fde7de50109f61f [file] [log] [blame]
Duncan Laurie645b3762013-02-12 14:00:47 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Duncan Laurie645b3762013-02-12 14:00:47 -080015 */
16
17#include <console/console.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
21#include "pch.h"
Kyösti Mälkkie2227a22014-02-05 13:02:55 +020022#include <device/pci_ehci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020023#include <device/pci_ops.h>
Duncan Laurie645b3762013-02-12 14:00:47 -080024
25static void usb_xhci_init(struct device *dev)
26{
27 u32 reg32;
Vladimir Serbinenkob26156e2015-01-31 17:45:50 +010028 struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
Duncan Laurie645b3762013-02-12 14:00:47 -080029
30 printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
31
Nicolas Reinecke59aef5c2015-04-16 23:25:00 +020032 if (config->xhci_overcurrent_mapping)
33 pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
34
Duncan Laurie645b3762013-02-12 14:00:47 -080035 /* lock overcurrent map */
36 reg32 = pci_read_config32(dev, 0x44);
37 reg32 |= 1;
38 pci_write_config32(dev, 0x44, reg32);
39
Nicolas Reinecke0b29a7b2015-03-29 17:51:11 +020040 pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
41 pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);
Vladimir Serbinenkob26156e2015-01-31 17:45:50 +010042
Duncan Laurie645b3762013-02-12 14:00:47 -080043 /* Enable clock gating */
44 reg32 = pci_read_config32(dev, 0x40);
45 reg32 &= ~((1 << 20) | (1 << 21));
46 reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
47 reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
48 reg32 |= (1 << 31); /* lock */
49 pci_write_config32(dev, 0x40, reg32);
50
51 printk(BIOS_DEBUG, "done.\n");
52}
53
Aaron Durbinaa090cb2017-09-13 16:01:52 -060054static const char *xhci_acpi_name(const struct device *dev)
Patrick Rudolph604f6982017-06-07 09:46:52 +020055{
56 return "XHC";
57}
58
Duncan Laurie645b3762013-02-12 14:00:47 -080059static struct pci_operations xhci_pci_ops = {
Subrata Banik4a0f0712019-03-20 14:29:47 +053060 .set_subsystem = pci_dev_set_subsystem,
Duncan Laurie645b3762013-02-12 14:00:47 -080061};
62
63static struct device_operations usb_xhci_ops = {
64 .read_resources = pci_dev_read_resources,
65 .set_resources = pci_dev_set_resources,
66 .enable_resources = pci_dev_enable_resources,
67 .init = usb_xhci_init,
68 .scan_bus = 0,
69 .ops_pci = &xhci_pci_ops,
Patrick Rudolph604f6982017-06-07 09:46:52 +020070 .acpi_name = xhci_acpi_name,
Duncan Laurie645b3762013-02-12 14:00:47 -080071};
72
73static const unsigned short pci_device_ids[] = { 0x1e31, 0 };
74
75static const struct pci_driver pch_usb_xhci __pci_driver = {
76 .ops = &usb_xhci_ops,
77 .vendor = PCI_VENDOR_ID_INTEL,
78 .devices = pci_device_ids,
79};