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review.coreboot.org / coreboot / 1222a73205bd3a0faba988411b4aec6ea8de1059 / . / src / soc / intel / skylake / vr_config.c
blob: 17ccd7dd937cf060153ad385c04a7dad3bc521be [file] [log] [blame]
Aaron Durbindf214402015-12-14 16:44:26 -0600[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Rizwan Qureshi1222a732016-08-23 14:31:23 +0530[diff] [blame^]17#include <fsp/api.h>
18#include <soc/ramstage.h>
Aaron Durbindf214402015-12-14 16:44:26 -0600[diff] [blame]19#include <soc/vr_config.h>
20
21/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
22static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
23 [VR_SYSTEM_AGENT] = {
24 .vr_config_enable = 1,
25 .psi1threshold = VR_CFG_AMP(20),
26 .psi2threshold = VR_CFG_AMP(4),
27 .psi3threshold = VR_CFG_AMP(1),
28 .psi3enable = 0,
29 .psi4enable = 0,
30 .imon_slope = 0x0,
31 .imon_offset = 0x0,
32 .icc_max = VR_CFG_AMP(7),
33 .voltage_limit = 1520,
34 },
35 [VR_IA_CORE] = {
36 .vr_config_enable = 1,
37 .psi1threshold = VR_CFG_AMP(20),
38 .psi2threshold = VR_CFG_AMP(5),
39 .psi3threshold = VR_CFG_AMP(1),
40 .psi3enable = 0,
41 .psi4enable = 0,
42 .imon_slope = 0x0,
43 .imon_offset = 0x0,
44 .icc_max = VR_CFG_AMP(34),
45 .voltage_limit = 1520,
46 },
47 [VR_RING] = {
48 .vr_config_enable = 1,
49 .psi1threshold = VR_CFG_AMP(20),
50 .psi2threshold = VR_CFG_AMP(5),
51 .psi3threshold = VR_CFG_AMP(1),
52 .psi3enable = 0,
53 .psi4enable = 0,
54 .imon_slope = 0x0,
55 .imon_offset = 0x0,
56 .icc_max = VR_CFG_AMP(34),
57 .voltage_limit = 1520,
58 },
59 [VR_GT_UNSLICED] = {
60 .vr_config_enable = 1,
61 .psi1threshold = VR_CFG_AMP(20),
62 .psi2threshold = VR_CFG_AMP(5),
63 .psi3threshold = VR_CFG_AMP(1),
64 .psi3enable = 0,
65 .psi4enable = 0,
66 .imon_slope = 0x0,
67 .imon_offset = 0x0,
68 .icc_max = VR_CFG_AMP(35),
69 .voltage_limit = 1520,
70 },
71 [VR_GT_SLICED] = {
72 .vr_config_enable = 1,
73 .psi1threshold = VR_CFG_AMP(20),
74 .psi2threshold = VR_CFG_AMP(5),
75 .psi3threshold = VR_CFG_AMP(1),
76 .psi3enable = 0,
77 .psi4enable = 0,
78 .imon_slope = 0x0,
79 .imon_offset = 0x0,
80 .icc_max = VR_CFG_AMP(35),
81 .voltage_limit = 1520,
82 },
83};
84
Rizwan Qureshi1222a732016-08-23 14:31:23 +0530[diff] [blame^]85void fill_vr_domain_config(void *params,
86 int domain, const struct vr_config *chip_cfg)
Aaron Durbindf214402015-12-14 16:44:26 -0600[diff] [blame]87{
Rizwan Qureshi1222a732016-08-23 14:31:23 +0530[diff] [blame^]88 FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
Aaron Durbindf214402015-12-14 16:44:26 -0600[diff] [blame]89 const struct vr_config *cfg;
90
91 if (domain < 0 || domain >= NUM_VR_DOMAINS)
92 return;
93
94 /* Use device tree override if requested. */
95 if (chip_cfg->vr_config_enable)
96 cfg = chip_cfg;
97 else
98 cfg = &default_configs[domain];
99
Rizwan Qureshi1222a732016-08-23 14:31:23 +0530[diff] [blame^]100 vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
101 vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
102 vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
103 vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
104 vr_params->Psi3Enable[domain] = cfg->psi3enable;
105 vr_params->Psi4Enable[domain] = cfg->psi4enable;
106 vr_params->ImonSlope[domain] = cfg->imon_slope;
107 vr_params->ImonOffset[domain] = cfg->imon_offset;
108 vr_params->IccMax[domain] = cfg->icc_max;
109 vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
Aaron Durbindf214402015-12-14 16:44:26 -0600[diff] [blame]110}