Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Keith Hui | d0301c1 | 2017-09-02 18:13:11 -0400 | [diff] [blame] | 3 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 4 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Keith Hui | d0301c1 | 2017-09-02 18:13:11 -0400 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <commonlib/helpers.h> |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
| 9 | #include <program_loading.h> |
Keith Hui | d0301c1 | 2017-09-02 18:13:11 -0400 | [diff] [blame] | 10 | #include "i440bx.h" |
| 11 | |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 12 | void *cbmem_top_chipset(void) |
Keith Hui | d0301c1 | 2017-09-02 18:13:11 -0400 | [diff] [blame] | 13 | { |
| 14 | /* Base of TSEG is top of usable DRAM */ |
| 15 | /* |
| 16 | * SMRAM - System Management RAM Control Register |
| 17 | * 0x72 |
| 18 | * [7:4] Not relevant to this function. |
| 19 | * [3:3] Global SMRAM Enable (G_SMRAME) |
| 20 | * [2:0] Hardwired to 010. |
| 21 | * |
| 22 | * ESMRAMC - Extended System Management RAM Control |
| 23 | * 0x73 |
| 24 | * [7:7] H_SMRAM_EN |
| 25 | * 1 = When G_SMRAME=1, High SMRAM space is enabled at |
| 26 | * 0x100A0000-0x100FFFFF and forwarded to DRAM address |
| 27 | * 0x000A0000-0x000FFFFF. |
| 28 | * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at |
| 29 | * 0x000A0000-0x000BFFFF. |
| 30 | * [6:3] Not relevant to this function. |
| 31 | * [2:1] TSEG Size (T_SZ) |
| 32 | * Selects the size of the TSEG memory block, if enabled. |
| 33 | * 00 = 128KiB |
| 34 | * 01 = 256KiB |
| 35 | * 10 = 512KiB |
| 36 | * 11 = 1MiB |
| 37 | * [0:0] TSEG_EN |
| 38 | * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to |
| 39 | * appear between DRAM address (TOM-<TSEG Size>) to TOM. |
| 40 | * |
| 41 | * Source: 440BX datasheet, pages 3-28 thru 3-29. |
| 42 | */ |
| 43 | unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; |
| 44 | |
| 45 | int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; |
| 46 | /* T_SZ and TSEG_EN */ |
| 47 | int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; |
| 48 | if ((tseg & 0x1) && gsmrame) { |
| 49 | int tseg_size = 128 * KiB * (1 << (tseg >> 1)); |
| 50 | tom -= tseg_size; |
| 51 | } |
| 52 | return (void *)tom; |
| 53 | } |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 54 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 55 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 56 | { |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 57 | uintptr_t top_of_ram; |
| 58 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 59 | /* Cache CBMEM region as WB. */ |
| 60 | top_of_ram = (uintptr_t)cbmem_top(); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 61 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 62 | MTRR_TYPE_WRBACK); |
| 63 | |
Kyösti Mälkki | 54d6a28 | 2018-05-25 06:03:14 +0300 | [diff] [blame] | 64 | } |