| Keith Hui | d0301c1 | 2017-09-02 18:13:11 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Keith Hui <buurin@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <cbmem.h> |
| 20 | #include <commonlib/helpers.h> |
| 21 | #include "i440bx.h" |
| 22 | |
| 23 | void *cbmem_top(void) |
| 24 | { |
| 25 | /* Base of TSEG is top of usable DRAM */ |
| 26 | /* |
| 27 | * SMRAM - System Management RAM Control Register |
| 28 | * 0x72 |
| 29 | * [7:4] Not relevant to this function. |
| 30 | * [3:3] Global SMRAM Enable (G_SMRAME) |
| 31 | * [2:0] Hardwired to 010. |
| 32 | * |
| 33 | * ESMRAMC - Extended System Management RAM Control |
| 34 | * 0x73 |
| 35 | * [7:7] H_SMRAM_EN |
| 36 | * 1 = When G_SMRAME=1, High SMRAM space is enabled at |
| 37 | * 0x100A0000-0x100FFFFF and forwarded to DRAM address |
| 38 | * 0x000A0000-0x000FFFFF. |
| 39 | * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at |
| 40 | * 0x000A0000-0x000BFFFF. |
| 41 | * [6:3] Not relevant to this function. |
| 42 | * [2:1] TSEG Size (T_SZ) |
| 43 | * Selects the size of the TSEG memory block, if enabled. |
| 44 | * 00 = 128KiB |
| 45 | * 01 = 256KiB |
| 46 | * 10 = 512KiB |
| 47 | * 11 = 1MiB |
| 48 | * [0:0] TSEG_EN |
| 49 | * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to |
| 50 | * appear between DRAM address (TOM-<TSEG Size>) to TOM. |
| 51 | * |
| 52 | * Source: 440BX datasheet, pages 3-28 thru 3-29. |
| 53 | */ |
| 54 | unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; |
| 55 | |
| 56 | int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; |
| 57 | /* T_SZ and TSEG_EN */ |
| 58 | int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; |
| 59 | if ((tseg & 0x1) && gsmrame) { |
| 60 | int tseg_size = 128 * KiB * (1 << (tseg >> 1)); |
| 61 | tom -= tseg_size; |
| 62 | } |
| 63 | return (void *)tom; |
| 64 | } |