| Martin Roth | 7d86f34 | 2024-02-16 11:04:02 -0700 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 3 | config SOC_AMD_COMMON_BLOCK_LPC |
| 4 | bool |
| Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 5 | help |
| 6 | Select this option to use the traditional LPC-ISA bridge at D14F3. |
| Raul E Rangel | 314c716 | 2020-05-01 14:04:08 -0600 | [diff] [blame] | 7 | |
| 8 | config PROVIDES_ROM_SHARING |
| 9 | bool |
| Raul E Rangel | 314c716 | 2020-05-01 14:04:08 -0600 | [diff] [blame] | 10 | help |
| 11 | Select this option if the LPC bridge supports ROM sharing. |
| Furquan Shaikh | efe27cf | 2020-05-04 20:59:23 -0700 | [diff] [blame] | 12 | |
| Raul E Rangel | 3ba2180 | 2021-06-24 17:03:35 -0600 | [diff] [blame] | 13 | config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 14 | bool |
| 15 | select X86_CUSTOM_BOOTMEDIA |
| Karthikeyan Ramasubramanian | 953f2ad | 2021-07-28 23:41:42 -0600 | [diff] [blame] | 16 | select SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST |
| Raul E Rangel | d373d5d | 2021-06-25 11:07:23 -0600 | [diff] [blame] | 17 | depends on !SOC_AMD_PICASSO && !SOC_AMD_STONEYRIDGE |
| Raul E Rangel | 3ba2180 | 2021-06-24 17:03:35 -0600 | [diff] [blame] | 18 | help |
| 19 | Select this option to enable SPI DMA support. |
| 20 | |
| Raul E Rangel | c0025c2 | 2021-11-10 13:09:20 -0700 | [diff] [blame] | 21 | # The LPC SPI DMA controller requires the source and destination to be 64 byte |
| Raul E Rangel | cf17cd8 | 2021-07-23 16:43:18 -0600 | [diff] [blame] | 22 | # aligned. |
| 23 | config CBFS_CACHE_ALIGN |
| 24 | int |
| 25 | default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 26 | |
| Raul E Rangel | c0025c2 | 2021-11-10 13:09:20 -0700 | [diff] [blame] | 27 | config FSP_ALIGNMENT_FSP_S |
| 28 | int |
| 29 | default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 30 | |
| 31 | config FSP_ALIGNMENT_FSP_M |
| 32 | int |
| 33 | default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 34 | |
| Furquan Shaikh | efe27cf | 2020-05-04 20:59:23 -0700 | [diff] [blame] | 35 | config SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| 36 | bool |
| Furquan Shaikh | efe27cf | 2020-05-04 20:59:23 -0700 | [diff] [blame] | 37 | help |
| 38 | Select this option if platform supports eSPI using D14F3 configuration |
| 39 | registers. |
| 40 | |
| Felix Held | 62d42c3 | 2022-05-04 19:04:33 +0200 | [diff] [blame] | 41 | config SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES |
| 42 | bool |
| 43 | depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| 44 | help |
| 45 | Select this if the platform supports 16 instead of 4 eSPI IO decode |
| 46 | ranges and 5 instead of 4 eSPI MMIO decode ranges. |
| 47 | |
| Raul E Rangel | dbeae6a | 2022-04-25 13:32:35 -0600 | [diff] [blame] | 48 | config SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE |
| 49 | bool |
| 50 | depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| 51 | help |
| 52 | Selected by the SoC if it supports the ALERT_ENABLE bit. |
| 53 | |
| Furquan Shaikh | efe27cf | 2020-05-04 20:59:23 -0700 | [diff] [blame] | 54 | config SOC_AMD_COMMON_BLOCK_USE_ESPI |
| 55 | bool |
| 56 | depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| Furquan Shaikh | efe27cf | 2020-05-04 20:59:23 -0700 | [diff] [blame] | 57 | help |
| 58 | Select this option if mainboard uses eSPI instead of LPC (if supported |
| 59 | by platform). |
| Karthikeyan Ramasubramanian | 284831e | 2022-03-25 10:21:03 -0600 | [diff] [blame] | 60 | |
| 61 | config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN |
| 62 | bool |
| 63 | depends on SOC_AMD_COMMON_BLOCK_USE_ESPI |
| 64 | help |
| 65 | SMU will lock up at times if the port80h enable bit is cleared. Select |
| 66 | this option to retain the port80 enable bit while clearing other enable |
| 67 | bits in the ESPI Decode register. |