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Angel Pons89ab2502020-04-03 01:22:28 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Sven Schnellee2ca71e2011-02-14 20:02:47 +00002
3#include <device/device.h>
Sven Schnellee2ca71e2011-02-14 20:02:47 +00004#include <arch/smp/mpspec.h>
5#include <arch/ioapic.h>
Sven Schnellee2ca71e2011-02-14 20:02:47 +00006
7static void *smp_write_config_table(void *v)
8{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +02009 struct mp_config_table *mc;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000010 int isa_bus;
11
Elyes HAOUAS8da96e52016-09-22 21:20:54 +020012 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000013
Kyösti Mälkkidea42e02021-05-31 20:26:16 +030014 mptable_init(mc);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000015
Elyes HAOUAS8da96e52016-09-22 21:20:54 +020016 smp_write_processors(mc);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000017
18 mptable_write_buses(mc, NULL, &isa_bus);
19
20 /* I/O APICs: APIC ID Version State Address */
Felix Held0d192892024-02-06 16:55:29 +010021 u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000022
23 /* Legacy Interrupts */
Kyösti Mälkki860cff92021-06-07 22:20:57 +030024 mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000025
26 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
27 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
Kyösti Mälkki860cff92021-06-07 22:20:57 +030028 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, ioapic_id, 0x10); /* PCIe root 0.01.0 */
29 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, ioapic_id, 0x10); /* VGA 0.02.0 */
30 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, ioapic_id, 0x11); /* HD Audio 0:1b.0 */
31 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, ioapic_id, 0x14); /* PCIe 0:1c.0 */
32 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, ioapic_id, 0x15); /* PCIe 0:1c.1 */
33 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, ioapic_id, 0x16); /* PCIe 0:1c.2 */
34 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, ioapic_id, 0x17); /* PCIe 0:1c.3 */
35 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, ioapic_id, 0x10); /* USB 0:1d.0 */
36 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, ioapic_id, 0x11); /* USB 0:1d.1 */
37 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, ioapic_id, 0x12); /* USB 0:1d.2 */
38 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, ioapic_id, 0x13); /* USB 0:1d.3 */
39 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, ioapic_id, 0x17); /* LPC 0:1f.0 */
40 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, ioapic_id, 0x10); /* IDE 0:1f.1 */
41 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, ioapic_id, 0x10); /* SATA 0:1f.2 */
42 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x00, ioapic_id, 0x10); /* Cardbus 5:00.0 */
43 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x01, ioapic_id, 0x11); /* Firewire 5:00.1 */
44 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x02, ioapic_id, 0x12); /* SDHC 5:00.2 */
Sven Schnellee2ca71e2011-02-14 20:02:47 +000045
Sven Schnellef03dff72012-06-24 10:02:22 +020046 mptable_lintsrc(mc, isa_bus);
Patrick Georgib0a9c5c2011-10-07 23:01:55 +020047 return mptable_finalize(mc);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000048}
49
50unsigned long write_smp_table(unsigned long addr)
51{
52 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +020053 v = smp_write_floating_table(addr, 0);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000054 return (unsigned long)smp_write_config_table(v);
55}