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review.coreboot.org / coreboot / 89ab2503c9ec1528e29f7671bd12ce4a03cedf67 / . / src / mainboard / lenovo / x60 / mptable.c
blob: f3d9cfcdeae91dcec1e04954fed936e854065d52 [file] [log] [blame]
Angel Pons89ab2502020-04-03 01:22:28 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]3
4#include <device/device.h>
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]5#include <arch/smp/mpspec.h>
6#include <arch/ioapic.h>
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]7#include <stdint.h>
8
9static void *smp_write_config_table(void *v)
10{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]11 struct mp_config_table *mc;
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]12 int isa_bus;
13
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]14 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]15
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]16 mptable_init(mc, LOCAL_APIC_ADDR);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]17
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]18 smp_write_processors(mc);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]19
20 mptable_write_buses(mc, NULL, &isa_bus);
21
22 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]23 smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]24
25 /* Legacy Interrupts */
26 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
27
28 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
29 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
Kyösti Mälkkic32a92e2019-01-04 06:02:22 +0200[diff] [blame]30 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */
31 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */
32 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */
33 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */
34 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */
35 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */
36 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */
37 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */
38 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */
39 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */
40 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */
41 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */
42 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */
43 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */
44 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */
45 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x01, 0x02, 0x11); /* Firewire 5:00.1 */
46 smp_write_pci_intsrc(mc, mp_INT, 0x05, 0x00, 0x02, 0x02, 0x12); /* SDHC 5:00.2 */
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]47
Sven Schnellef03dff72012-06-24 10:02:22 +0200[diff] [blame]48 mptable_lintsrc(mc, isa_bus);
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]49 return mptable_finalize(mc);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]50}
51
52unsigned long write_smp_table(unsigned long addr)
53{
54 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]55 v = smp_write_floating_table(addr, 0);
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000[diff] [blame]56 return (unsigned long)smp_write_config_table(v);
57}