Angel Pons | 89ab250 | 2020-04-03 01:22:28 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 2 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 3 | #include <bootblock_common.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 4 | #include <delay.h> |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 5 | #include <stdint.h> |
| 6 | #include <device/pnp_def.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 7 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 9 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 10 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 11 | #include <southbridge/intel/common/gpio.h> |
Sven Schnelle | fea6bd1 | 2011-04-01 07:28:56 +0000 | [diff] [blame] | 12 | #include "dock.h" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 13 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 14 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 15 | void mainboard_lpc_decode(void) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 16 | { |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 17 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 18 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 19 | } |
| 20 | |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 21 | static void early_superio_config(void) |
| 22 | { |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 23 | int timeout = 100000; |
Elyes HAOUAS | efc3d04 | 2020-04-08 12:15:16 +0200 | [diff] [blame] | 24 | const pnp_devfn_t dev = PNP_DEV(0x2e, 3); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 25 | |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 26 | pnp_write_config(dev, 0x29, 0x06); |
| 27 | |
Paul Menzel | c2f1777 | 2013-04-29 23:05:44 +0200 | [diff] [blame] | 28 | while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 29 | udelay(1000); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 30 | |
| 31 | /* Enable COM1 */ |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 32 | pnp_set_logical_device(dev); |
| 33 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 34 | pnp_set_enable(dev, 1); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 35 | } |
| 36 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 37 | void bootblock_mainboard_early_init(void) |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 38 | { |
| 39 | /* Set up GPIO's early since it is needed for dock init */ |
| 40 | i82801gx_setup_bars(); |
| 41 | setup_pch_gpios(&mainboard_gpio_map); |
| 42 | |
| 43 | dlpc_init(); |
| 44 | /* dock_init initializes the DLPC switch on |
| 45 | * thinpad side, so this is required even |
| 46 | * if we're undocked. |
| 47 | */ |
| 48 | if (dock_present()) { |
| 49 | dock_connect(); |
| 50 | early_superio_config(); |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | void mainboard_late_rcba_config(void) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 55 | { |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 56 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 57 | RCBA32(D31IP) = 0x00001230; |
| 58 | RCBA32(D29IP) = 0x40004321; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 59 | |
| 60 | /* PCIe Interrupts */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 61 | RCBA32(D28IP) = 0x00004321; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 62 | /* HD Audio Interrupt */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 63 | RCBA32(D27IP) = 0x00000002; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 64 | |
| 65 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 66 | RCBA16(D31IR) = 0x1007; |
| 67 | RCBA16(D30IR) = 0x0076; |
| 68 | RCBA16(D29IR) = 0x3210; |
| 69 | RCBA16(D28IR) = 0x7654; |
| 70 | RCBA16(D27IR) = 0x0010; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 71 | |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 72 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 73 | RCBA32(FD) |= FD_INTLAN; |
Sven Schnelle | ddb3f0a | 2011-02-16 13:12:41 +0000 | [diff] [blame] | 74 | |
Sven Schnelle | ddb3f0a | 2011-02-16 13:12:41 +0000 | [diff] [blame] | 75 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
Peter Lemenkov | 522a1b5 | 2019-01-10 12:19:01 +0100 | [diff] [blame] | 76 | RCBA64(IOTR3) = 0x000200f0000c0801ULL; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 79 | void mainboard_get_spd_map(u8 spd_map[4]) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 80 | { |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 81 | spd_map[0] = 0x50; |
| 82 | spd_map[2] = 0x51; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 83 | } |