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Angel Pons89ab2502020-04-03 01:22:28 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Sven Schnellee2ca71e2011-02-14 20:02:47 +00002
Arthur Heymansc5839202019-11-12 23:48:42 +01003#include <bootblock_common.h>
Kyösti Mälkki7fbed222019-07-11 08:14:07 +03004#include <delay.h>
Arthur Heymansdc584c32019-11-12 20:37:21 +01005#include <stdint.h>
6#include <device/pnp_def.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +02007#include <device/pnp_ops.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02008#include <device/pci_ops.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +11009#include <northbridge/intel/i945/i945.h>
Edward O'Callaghan77757c22015-01-04 21:33:39 +110010#include <southbridge/intel/i82801gx/i82801gx.h>
Arthur Heymans62902ca2016-11-29 14:13:43 +010011#include <southbridge/intel/common/gpio.h>
Sven Schnellefea6bd12011-04-01 07:28:56 +000012#include "dock.h"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000013
Arthur Heymansfecf7772019-11-09 14:19:04 +010014/* Override the default lpc decode ranges */
Arthur Heymansdc584c32019-11-12 20:37:21 +010015void mainboard_lpc_decode(void)
Sven Schnellee2ca71e2011-02-14 20:02:47 +000016{
Sven Schnellee2ca71e2011-02-14 20:02:47 +000017 // decode range
Arthur Heymansb451df22017-08-15 20:59:09 +020018 pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000019}
20
Sven Schnellee2ca71e2011-02-14 20:02:47 +000021static void early_superio_config(void)
22{
Sven Schnelledf6fd562011-04-05 13:00:33 +000023 int timeout = 100000;
Elyes HAOUASefc3d042020-04-08 12:15:16 +020024 const pnp_devfn_t dev = PNP_DEV(0x2e, 3);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000025
Sven Schnelledf6fd562011-04-05 13:00:33 +000026 pnp_write_config(dev, 0x29, 0x06);
27
Paul Menzelc2f17772013-04-29 23:05:44 +020028 while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
Sven Schnelledf6fd562011-04-05 13:00:33 +000029 udelay(1000);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000030
31 /* Enable COM1 */
Sven Schnelledf6fd562011-04-05 13:00:33 +000032 pnp_set_logical_device(dev);
33 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
34 pnp_set_enable(dev, 1);
Sven Schnellee2ca71e2011-02-14 20:02:47 +000035}
36
Arthur Heymansc5839202019-11-12 23:48:42 +010037void bootblock_mainboard_early_init(void)
Arthur Heymansdc584c32019-11-12 20:37:21 +010038{
39 /* Set up GPIO's early since it is needed for dock init */
40 i82801gx_setup_bars();
41 setup_pch_gpios(&mainboard_gpio_map);
42
43 dlpc_init();
44 /* dock_init initializes the DLPC switch on
45 * thinpad side, so this is required even
46 * if we're undocked.
47 */
48 if (dock_present()) {
49 dock_connect();
50 early_superio_config();
51 }
52}
53
54void mainboard_late_rcba_config(void)
Sven Schnellee2ca71e2011-02-14 20:02:47 +000055{
Sven Schnellee2ca71e2011-02-14 20:02:47 +000056 /* Device 1f interrupt pin register */
Arthur Heymansb451df22017-08-15 20:59:09 +020057 RCBA32(D31IP) = 0x00001230;
58 RCBA32(D29IP) = 0x40004321;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000059
60 /* PCIe Interrupts */
Arthur Heymansb451df22017-08-15 20:59:09 +020061 RCBA32(D28IP) = 0x00004321;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000062 /* HD Audio Interrupt */
Arthur Heymansb451df22017-08-15 20:59:09 +020063 RCBA32(D27IP) = 0x00000002;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000064
65 /* dev irq route register */
Arthur Heymansb451df22017-08-15 20:59:09 +020066 RCBA16(D31IR) = 0x1007;
67 RCBA16(D30IR) = 0x0076;
68 RCBA16(D29IR) = 0x3210;
69 RCBA16(D28IR) = 0x7654;
70 RCBA16(D27IR) = 0x0010;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000071
Sven Schnellee2ca71e2011-02-14 20:02:47 +000072 /* Disable unused devices */
Arthur Heymans6267f5d2018-12-15 23:46:48 +010073 RCBA32(FD) |= FD_INTLAN;
Sven Schnelleddb3f0a2011-02-16 13:12:41 +000074
Sven Schnelleddb3f0a2011-02-16 13:12:41 +000075 /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
Peter Lemenkov522a1b52019-01-10 12:19:01 +010076 RCBA64(IOTR3) = 0x000200f0000c0801ULL;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000077}
78
Arthur Heymansdc584c32019-11-12 20:37:21 +010079void mainboard_get_spd_map(u8 spd_map[4])
Sven Schnellee2ca71e2011-02-14 20:02:47 +000080{
Arthur Heymansdc584c32019-11-12 20:37:21 +010081 spd_map[0] = 0x50;
82 spd_map[2] = 0x51;
Sven Schnellee2ca71e2011-02-14 20:02:47 +000083}