Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 18 | #include <bootblock_common.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 19 | #include <delay.h> |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <device/pnp_def.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 22 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 24 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 26 | #include <southbridge/intel/common/gpio.h> |
Sven Schnelle | fea6bd1 | 2011-04-01 07:28:56 +0000 | [diff] [blame] | 27 | #include "dock.h" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 28 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 29 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 30 | void mainboard_lpc_decode(void) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 31 | { |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 32 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 33 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 34 | } |
| 35 | |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 36 | static void early_superio_config(void) |
| 37 | { |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 38 | int timeout = 100000; |
Antonello Dettori | 4bf48e8 | 2016-08-30 22:15:49 +0200 | [diff] [blame] | 39 | pnp_devfn_t dev = PNP_DEV(0x2e, 3); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 40 | |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 41 | pnp_write_config(dev, 0x29, 0x06); |
| 42 | |
Paul Menzel | c2f1777 | 2013-04-29 23:05:44 +0200 | [diff] [blame] | 43 | while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 44 | udelay(1000); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 45 | |
| 46 | /* Enable COM1 */ |
Sven Schnelle | df6fd56 | 2011-04-05 13:00:33 +0000 | [diff] [blame] | 47 | pnp_set_logical_device(dev); |
| 48 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 49 | pnp_set_enable(dev, 1); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 50 | } |
| 51 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame^] | 52 | void bootblock_mainboard_early_init(void) |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 53 | { |
| 54 | /* Set up GPIO's early since it is needed for dock init */ |
| 55 | i82801gx_setup_bars(); |
| 56 | setup_pch_gpios(&mainboard_gpio_map); |
| 57 | |
| 58 | dlpc_init(); |
| 59 | /* dock_init initializes the DLPC switch on |
| 60 | * thinpad side, so this is required even |
| 61 | * if we're undocked. |
| 62 | */ |
| 63 | if (dock_present()) { |
| 64 | dock_connect(); |
| 65 | early_superio_config(); |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | void mainboard_late_rcba_config(void) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 70 | { |
| 71 | /* Set up virtual channel 0 */ |
Peter Lemenkov | e232455 | 2018-10-23 11:17:32 +0200 | [diff] [blame] | 72 | RCBA32(V0CTL) = 0x80000001; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 73 | |
| 74 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 75 | RCBA32(D31IP) = 0x00001230; |
| 76 | RCBA32(D29IP) = 0x40004321; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 77 | |
| 78 | /* PCIe Interrupts */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 79 | RCBA32(D28IP) = 0x00004321; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 80 | /* HD Audio Interrupt */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 81 | RCBA32(D27IP) = 0x00000002; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 82 | |
| 83 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 84 | RCBA16(D31IR) = 0x1007; |
| 85 | RCBA16(D30IR) = 0x0076; |
| 86 | RCBA16(D29IR) = 0x3210; |
| 87 | RCBA16(D28IR) = 0x7654; |
| 88 | RCBA16(D27IR) = 0x0010; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 89 | |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 90 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 91 | RCBA32(FD) |= FD_INTLAN; |
Sven Schnelle | ddb3f0a | 2011-02-16 13:12:41 +0000 | [diff] [blame] | 92 | |
| 93 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
Peter Lemenkov | 522a1b5 | 2019-01-10 12:19:01 +0100 | [diff] [blame] | 94 | RCBA64(IOTR0) = 0x000200010000fe01ULL; |
Sven Schnelle | ddb3f0a | 2011-02-16 13:12:41 +0000 | [diff] [blame] | 95 | |
| 96 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
Peter Lemenkov | 522a1b5 | 2019-01-10 12:19:01 +0100 | [diff] [blame] | 97 | RCBA64(IOTR3) = 0x000200f0000c0801ULL; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 100 | |
| 101 | void mainboard_get_spd_map(u8 spd_map[4]) |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 102 | { |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 103 | spd_map[0] = 0x50; |
| 104 | spd_map[2] = 0x51; |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 105 | } |