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review.coreboot.org / coreboot / 0d19289e840f9c711f50a74437d1b3856222db03 / . / src / mainboard / ibase / mb899 / mptable.c
blob: bb4379685ef2a6afac573971d29e07f783d7bf75 [file] [log] [blame]
Angel Pons30a511c2020-04-03 01:22:09 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]2
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]3#include <device/device.h>
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]4#include <console/console.h>
5#include <arch/smp/mpspec.h>
Uwe Hermann74d1a6e2010-10-12 17:34:08 +0000[diff] [blame]6#include <arch/ioapic.h>
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]7
8static void *smp_write_config_table(void *v)
9{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]10 struct mp_config_table *mc;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]11 struct device *riser = NULL, *firewire = NULL;
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]12 int firewire_bus = 0, riser_bus = 0, isa_bus;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]13
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]14 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]15
Kyösti Mälkkidea42e02021-05-31 20:26:16 +0300[diff] [blame]16 mptable_init(mc);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]17
Elyes HAOUAS8da96e52016-09-22 21:20:54 +0200[diff] [blame]18 smp_write_processors(mc);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]19
20 firewire = dev_find_device(0x104c, 0x8023, 0);
21 if (firewire) {
Arthur Heymans7fcd4d52023-08-24 15:12:19 +0200[diff] [blame]22 firewire_bus = firewire->upstream->secondary;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]23 printk(BIOS_SPEW, "Firewire device is on bus %x\n",
24 firewire_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]25 }
26
27 // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
28 // highest bus number on the pci bus.
29 riser = dev_find_device(0x3388, 0x0021, 0);
30 if (!riser)
31 riser = dev_find_device(0x3388, 0x0022, 0);
32 if (riser) {
Arthur Heymans7fcd4d52023-08-24 15:12:19 +0200[diff] [blame]33 riser_bus = riser->downstream->secondary;
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]34 printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]35 }
36
Patrick Georgi5244e1b2010-11-21 14:41:07 +0000[diff] [blame]37 mptable_write_buses(mc, NULL, &isa_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]38
39 /* I/O APICs: APIC ID Version State Address */
Felix Held0d192892024-02-06 16:55:29 +0100[diff] [blame^]40 u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]41
42 /* Legacy Interrupts */
43
44 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
45 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
Kyösti Mälkki860cff92021-06-07 22:20:57 +0300[diff] [blame]46 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
47 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
48 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
49 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
50 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
51 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
52 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
53 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
54 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
55 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
56 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
57 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]58
59 /* Builtin devices on Bus 0 */
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]60 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x01, 0, ioapic_id, 0x10);
61 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
62 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
63 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
64 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
65 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
66 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
67 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
68 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
69 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]70
71 /* Internal PCI bus (Firewire, PCI slot) */
72 if (firewire) {
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]73 smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x00, 0, ioapic_id, 0x10);
74 smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x01, 0, ioapic_id, 0x14);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]75 }
76
77 if (riser) {
78 /* Old riser card */
79 // riser slot top 5:8.0
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]80 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x08, 0, ioapic_id, 0x14);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]81 // riser slot middle 5:9.0
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]82 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x09, 0, ioapic_id, 0x15);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]83 // riser slot bottom 5:a.0
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]84 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0a, 0, ioapic_id, 0x16);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]85
86 /* New Riser Card */
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]87 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0c, 0, ioapic_id, 0x14);
88 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0d, 0, ioapic_id, 0x15);
89 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0e, 0, ioapic_id, 0x16);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]90 }
91
92 /* PCIe slot */
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]93 smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
94 smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 1, ioapic_id, 0x11);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]95
96 /* Onboard Ethernet */
Kyösti Mälkki7742aed2021-06-07 22:18:35 +0300[diff] [blame]97 smp_write_pci_intsrc(mc, mp_INT, 0x2, 0x00, 0, ioapic_id, 0x10);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]98
99 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +0200[diff] [blame]100 mptable_lintsrc(mc, isa_bus);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]101
102 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]103 return mptable_finalize(mc);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]104}
105
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]106unsigned long write_smp_table(unsigned long addr)
107{
108 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]109 v = smp_write_floating_table(addr, 1);
Bernhard M. Wiedemann6e554de2010-05-30 12:56:17 +0000[diff] [blame]110 return (unsigned long)smp_write_config_table(v);
111}