blob: 389b84205d051e40a6139177b7eabcb2e5ac94d5 [file] [log] [blame]
Dtrain Hsua6d337b2023-05-18 17:28:42 +08001fw_config
Dtrain Hsu764167b2023-05-18 17:34:56 +08002 field DB_LTE 1 1
3 option LTE_ABSENT 0
4 option LTE_PRESENT 1
5 end
Dtrain Hsu9be583e2023-05-18 17:32:01 +08006 field TOUCHPAD 8 9
7 option TOUCHPAD_UNKNOWN 0
8 option TOUCHPAD_EKT3744 1
9 option TOUCHPAD_GT7863 2
10 end
Dtrain Hsua6d337b2023-05-18 17:28:42 +080011 field TOUCHSCREEN 10 12
12 option TOUCHSCREEN_UNKNOWN 0
13 option TOUCHSCREEN_NONE 1
14 option TOUCHSCREEN_EKTH7D18 2
15 option TOUCHSCREEN_GT7996F 3
16 option TOUCHSCREEN_EKTH5012 4
17 option TOUCHSCREEN_WDT8752A 5
18 option TOUCHSCREEN_GTCH7502 6
Dtrain Hsu5879b612023-08-31 17:36:08 +080019 option TOUCHSCREEN_WDT8790A 7
Dtrain Hsua6d337b2023-05-18 17:28:42 +080020 end
Dtrain Hsu22c616e2023-07-13 11:22:54 +080021 field EXT_VR 14 14
22 option EXT_VR_PRESENT 0
23 option EXT_VR_ABSENT 1
24 end
Dtrain Hsua6d337b2023-05-18 17:28:42 +080025end
26
van_chene5fa3b12023-03-13 14:57:00 +080027chip soc/intel/alderlake
Van Chendea2c472023-03-21 09:34:18 +080028 register "sagv" = "SaGv_Enabled"
van_chene5fa3b12023-03-13 14:57:00 +080029
Dtrain Hsu995772f2023-05-03 17:24:16 +080030 # EMMC Tx CMD Delay
31 # Refer to EDS-Vol2-42.3.7.
32 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
33 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
34 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x00000505"
35
36 # EMMC TX DATA Delay 1
37 # Refer to EDS-Vol2-42.3.8.
38 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
39 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
Dtrain Hsu5ef37962023-05-26 13:54:05 +080040 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x00000909"
Dtrain Hsu995772f2023-05-03 17:24:16 +080041
42 # EMMC TX DATA Delay 2
43 # Refer to EDS-Vol2-42.3.9.
44 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
45 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
46 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
47 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
Dtrain Hsu5ef37962023-05-26 13:54:05 +080048 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1c272828"
Dtrain Hsu995772f2023-05-03 17:24:16 +080049
50 # EMMC RX CMD/DATA Delay 1
51 # Refer to EDS-Vol2-42.3.10.
52 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
53 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
54 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
55 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
Dtrain Hsu5ef37962023-05-26 13:54:05 +080056 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1c171835"
Dtrain Hsu995772f2023-05-03 17:24:16 +080057
58 # EMMC RX CMD/DATA Delay 2
59 # Refer to EDS-Vol2-42.3.12.
60 # [17:16] stands for Rx Clock before Output Buffer,
61 # 00: Rx clock after output buffer,
62 # 01: Rx clock before output buffer,
63 # 10: Automatic selection based on working mode.
64 # 11: Reserved
65 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
66 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
Dtrain Hsu5ef37962023-05-26 13:54:05 +080067 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x00010025"
Dtrain Hsu995772f2023-05-03 17:24:16 +080068
69 # EMMC Rx Strobe Delay
70 # Refer to EDS-Vol2-42.3.11.
71 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
72 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
Dtrain Hsu5ef37962023-05-26 13:54:05 +080073 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x00001111"
Dtrain Hsu995772f2023-05-03 17:24:16 +080074
Van Chendea2c472023-03-21 09:34:18 +080075 # SOC Aux orientation override:
76 # This is a bitfield that corresponds to up to 4 TCSS ports.
77 # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
78 # TcssAuxOri = 0101b
79 # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
80 # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
81 # motherboard to USBC connector
82
83 register "tcss_aux_ori" = "5"
84 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
85 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
86
87 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera
88 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
89
90 register "serial_io_i2c_mode" = "{
91 [PchSerialIoIndexI2C0] = PchSerialIoPci,
92 [PchSerialIoIndexI2C1] = PchSerialIoPci,
93 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
94 [PchSerialIoIndexI2C3] = PchSerialIoPci,
95 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
96 [PchSerialIoIndexI2C5] = PchSerialIoPci,
97 }"
98
Dtrain Hsueebf63c2023-06-27 10:50:51 +080099 register "tcc_offset" = "3"
100
Van Chendea2c472023-03-21 09:34:18 +0800101 # Intel Common SoC Config
102 #+-------------------+---------------------------+
103 #| Field | Value |
104 #+-------------------+---------------------------+
105 #| I2C0 | TPM. Early init is |
106 #| | required to set up a BAR |
107 #| | for TPM communication |
108 #| I2C1 | Touchscreen |
109 #| I2C2 | |
110 #| I2C3 | Audio |
111 #| I2C5 | Trackpad |
112 #+-------------------+---------------------------+
113 register "common_soc_config" = "{
114 .i2c[0] = {
115 .early_init = 1,
116 .speed = I2C_SPEED_FAST_PLUS,
117 .speed_config[0] = {
118 .speed = I2C_SPEED_FAST_PLUS,
119 .scl_lcnt = 55,
120 .scl_hcnt = 30,
121 .sda_hold = 7,
122 }
123 },
124 .i2c[1] = {
125 .speed = I2C_SPEED_FAST,
126 .speed_config[0] = {
127 .speed = I2C_SPEED_FAST,
128 .scl_lcnt = 158,
129 .scl_hcnt = 79,
130 .sda_hold = 7,
131 }
132 },
133 .i2c[3] = {
134 .speed = I2C_SPEED_FAST,
135 .speed_config[0] = {
136 .speed = I2C_SPEED_FAST,
137 .scl_lcnt = 158,
138 .scl_hcnt = 79,
139 .sda_hold = 7,
140 }
141 },
142 .i2c[5] = {
143 .speed = I2C_SPEED_FAST,
144 .speed_config[0] = {
145 .speed = I2C_SPEED_FAST,
146 .scl_lcnt = 158,
147 .scl_hcnt = 79,
148 .sda_hold = 7,
149 }
150 },
151 }"
152
153 device domain 0 on
Dtrain Hsu1b3b0982023-05-24 16:11:44 +0800154 device ref dtt on
155 chip drivers/intel/dptf
156 ## sensor information
157 register "options.tsr[0].desc" = ""CPU_VR""
158 register "options.tsr[1].desc" = ""Charger""
159 register "options.tsr[2].desc" = ""Ambient""
160
161 ## Passive Policy
162 register "policies.passive" = "{
163 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
164 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000),
165 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000),
166 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000),
167 }"
168 ## Critical Policy
169 register "policies.critical" = "{
Dtrain Hsueebf63c2023-06-27 10:50:51 +0800170 [0] = DPTF_CRITICAL(CPU, 130, SHUTDOWN),
171 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN),
172 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 105, SHUTDOWN),
173 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
Dtrain Hsu1b3b0982023-05-24 16:11:44 +0800174 }"
175
176 register "controls.power_limits" = "{
177 .pl1 = {
178 .min_power = 3000,
179 .max_power = 6000,
180 .time_window_min = 28 * MSECS_PER_SEC,
181 .time_window_max = 28 * MSECS_PER_SEC,
Dtrain Hsueebf63c2023-06-27 10:50:51 +0800182 .granularity = 125
Dtrain Hsu1b3b0982023-05-24 16:11:44 +0800183 },
184 .pl2 = {
185 .min_power = 25000,
186 .max_power = 25000,
187 .time_window_min = 28 * MSECS_PER_SEC,
188 .time_window_max = 28 * MSECS_PER_SEC,
189 .granularity = 1000
190 }
191 }"
192
193 ## Charger Performance Control (Control, mA)
194 register "controls.charger_perf" = "{
195 [0] = { 255, 1700 },
196 [1] = { 24, 1500 },
197 [2] = { 16, 1000 },
198 [3] = { 8, 500 }
199 }"
200 device generic 0 on end
201 end
202 end
Van Chendea2c472023-03-21 09:34:18 +0800203 device ref cnvi_wifi on
204 chip drivers/wifi/generic
205 register "wake" = "GPE0_PME_B0"
206 register "enable_cnvi_ddr_rfim" = "true"
Dtrain Hsu7a759082023-05-26 16:57:48 +0800207 register "add_acpi_dma_property" = "true"
Van Chendea2c472023-03-21 09:34:18 +0800208 device generic 0 on end
209 end
210 end
211 device ref i2c1 on
212 chip drivers/i2c/hid
213 register "generic.hid" = ""WDHT0002""
214 register "generic.desc" = ""WDT Touchscreen""
215 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
216 register "generic.detect" = "1"
217 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
218 register "generic.reset_delay_ms" = "20"
219 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
220 register "generic.stop_delay_ms" = "130"
221 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
222 register "generic.enable_delay_ms" = "1"
223 register "generic.has_power_resource" = "1"
224 register "hid_desc_reg_offset" = "0x20"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800225 device i2c 2c on
226 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
227 end
Van Chendea2c472023-03-21 09:34:18 +0800228 end
229 chip drivers/i2c/generic
230 register "hid" = ""ELAN0001""
231 register "desc" = ""ELAN Touchscreen""
232 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
233 register "detect" = "1"
234 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
235 register "reset_delay_ms" = "20"
236 register "reset_off_delay_ms" = "2"
237 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
238 register "stop_delay_ms" = "280"
239 register "stop_off_delay_ms" = "2"
240 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
241 register "enable_delay_ms" = "1"
242 register "has_power_resource" = "1"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800243 device i2c 10 on
244 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
245 end
Van Chendea2c472023-03-21 09:34:18 +0800246 end
247 chip drivers/i2c/hid
248 register "generic.hid" = ""ELAN900C""
249 register "generic.desc" = ""ELAN Touchscreen""
250 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
251 register "generic.detect" = "1"
252 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
Dtrain Hsu7ecc3662023-07-12 11:35:19 +0800253 register "generic.reset_delay_ms" = "6"
Van Chendea2c472023-03-21 09:34:18 +0800254 register "generic.reset_off_delay_ms" = "1"
255 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
256 register "generic.stop_delay_ms" = "300"
257 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
258 register "generic.enable_delay_ms" = "6"
259 register "generic.has_power_resource" = "1"
260 register "hid_desc_reg_offset" = "0x01"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800261 device i2c 16 on
262 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
263 end
Van Chendea2c472023-03-21 09:34:18 +0800264 end
265 chip drivers/i2c/hid
266 register "generic.hid" = ""GXTP7996""
267 register "generic.desc" = ""Goodix Touchscreen""
268 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
269 register "generic.detect" = "1"
270 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
271 register "generic.reset_delay_ms" = "100"
272 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
Dtrain Hsu77b71cf2023-07-18 14:14:41 +0800273 register "generic.stop_delay_ms" = "200"
Van Chendea2c472023-03-21 09:34:18 +0800274 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
275 register "generic.enable_delay_ms" = "10"
276 register "generic.has_power_resource" = "1"
277 register "hid_desc_reg_offset" = "0x01"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800278 device i2c 5d on
279 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
280 end
Van Chendea2c472023-03-21 09:34:18 +0800281 end
282 chip drivers/i2c/hid
283 register "generic.hid" = ""GTCH7502""
284 register "generic.desc" = ""G2TOUCH Touchscreen""
285 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
286 register "generic.detect" = "1"
287 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
288 register "generic.reset_delay_ms" = "100"
289 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
290 register "generic.stop_delay_ms" = "30"
291 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
292 register "generic.enable_delay_ms" = "30"
293 register "generic.has_power_resource" = "1"
294 register "hid_desc_reg_offset" = "0x01"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800295 device i2c 40 on
296 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
297 end
Van Chendea2c472023-03-21 09:34:18 +0800298 end
Dtrain Hsu5879b612023-08-31 17:36:08 +0800299 chip drivers/i2c/hid
300 register "generic.hid" = ""WDHT2601""
301 register "generic.desc" = ""WDT Touchscreen""
302 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
303 register "generic.detect" = "1"
304 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
305 register "generic.reset_delay_ms" = "20"
306 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
307 register "generic.stop_delay_ms" = "130"
308 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
309 register "generic.enable_delay_ms" = "1"
310 register "generic.has_power_resource" = "1"
311 register "hid_desc_reg_offset" = "0x20"
Dtrain Hsu0c8d64c2023-12-15 11:44:15 +0800312 device i2c 3c on
313 probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN
314 end
Dtrain Hsu5879b612023-08-31 17:36:08 +0800315 end
Van Chendea2c472023-03-21 09:34:18 +0800316 end
317 device ref i2c3 on
318 chip drivers/i2c/cs42l42
319 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
320 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)"
321 register "ts_inv" = "true"
322 register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
323 register "ts_dbnc_fall" = "FALL_DEB_0_MS"
324 register "btn_det_init_dbnce" = "100"
325 register "btn_det_event_dbnce" = "10"
326 register "bias_lvls[0]" = "15"
327 register "bias_lvls[1]" = "8"
328 register "bias_lvls[2]" = "4"
329 register "bias_lvls[3]" = "1"
330 register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
331 register "hs_bias_sense_disable" = "true"
332 device i2c 48 on end
333 end
334 end
335 device ref i2c5 on
336 chip drivers/i2c/generic
337 register "hid" = ""ELAN0000""
338 register "desc" = ""ELAN Touchpad""
339 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
340 register "wake" = "GPE0_DW2_14"
341 register "detect" = "1"
Dtrain Hsu57547492023-08-29 11:21:45 +0800342 device i2c 15 on end
Van Chendea2c472023-03-21 09:34:18 +0800343 end
344 chip drivers/i2c/hid
345 register "generic.hid" = ""GXTP7863""
346 register "generic.desc" = ""Goodix Touchpad""
347 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
348 register "generic.wake" = "GPE0_DW2_14"
349 register "generic.detect" = "1"
350 register "hid_desc_reg_offset" = "0x20"
Dtrain Hsu57547492023-08-29 11:21:45 +0800351 device i2c 2c on end
Van Chendea2c472023-03-21 09:34:18 +0800352 end
353 end
Dtrain Hsu16592182023-06-05 10:00:41 +0800354 device ref pcie_rp7 off end
Van Chendea2c472023-03-21 09:34:18 +0800355 device ref hda on
356 chip drivers/generic/max98357a
357 register "hid" = ""MX98360A""
358 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
359 register "sdmode_delay" = "5"
360 device generic 0 on end
361 end
Matt DeVillier189da312023-09-08 20:57:55 -0500362 chip drivers/sof
363 register "spkr_tplg" = "max98360a"
364 register "jack_tplg" = "cs42l42"
365 register "mic_tplg" = "_2ch_pdm0"
366 device generic 0 on end
367 end
Van Chendea2c472023-03-21 09:34:18 +0800368 end
369 device ref pch_espi on
370 chip ec/google/chromeec
371 use conn0 as mux_conn[0]
372 use conn1 as mux_conn[1]
373 device pnp 0c09.0 on end
374 end
375 end
376 device ref pmc hidden
377 chip drivers/intel/pmc_mux
378 device generic 0 on
379 chip drivers/intel/pmc_mux/conn
380 use usb2_port1 as usb2_port
381 use tcss_usb3_port1 as usb3_port
382 device generic 0 alias conn0 on end
383 end
384 chip drivers/intel/pmc_mux/conn
385 use usb2_port2 as usb2_port
386 use tcss_usb3_port2 as usb3_port
387 device generic 1 alias conn1 on end
388 end
389 end
390 end
391 end
392 device ref tcss_xhci on
393 chip drivers/usb/acpi
394 device ref tcss_root_hub on
395 chip drivers/usb/acpi
396 register "desc" = ""USB3 Type-C Port C0 (MLB)""
397 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
398 register "use_custom_pld" = "true"
399 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
400 device ref tcss_usb3_port1 on end
401 end
402 chip drivers/usb/acpi
403 register "desc" = ""USB3 Type-C Port C1 (DB)""
404 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
405 register "use_custom_pld" = "true"
406 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
407 device ref tcss_usb3_port2 on end
408 end
409 end
410 end
411 end
412 device ref xhci on
413 chip drivers/usb/acpi
414 device ref xhci_root_hub on
415 chip drivers/usb/acpi
416 register "desc" = ""USB2 Type-C Port C0 (MLB)""
417 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
418 register "use_custom_pld" = "true"
419 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
420 device ref usb2_port1 on end
421 end
422 chip drivers/usb/acpi
423 register "desc" = ""USB2 Type-C Port C1 (DB)""
424 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
425 register "use_custom_pld" = "true"
426 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
427 device ref usb2_port2 on end
428 end
429 chip drivers/usb/acpi
430 register "desc" = ""USB2 Type-A Port A0 (MLB)""
431 register "type" = "UPC_TYPE_A"
432 register "use_custom_pld" = "true"
433 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
434 device ref usb2_port3 on end
435 end
436 chip drivers/usb/acpi
437 register "desc" = ""USB2 WWAN""
438 register "type" = "UPC_TYPE_INTERNAL"
Dtrain Hsu764167b2023-05-18 17:34:56 +0800439 device ref usb2_port4 on
440 probe DB_LTE LTE_PRESENT
441 end
Van Chendea2c472023-03-21 09:34:18 +0800442 end
443 chip drivers/usb/acpi
444 register "desc" = ""USB2 User Facing Camera""
445 register "type" = "UPC_TYPE_INTERNAL"
446 device ref usb2_port6 on end
447 end
448 chip drivers/usb/acpi
449 register "desc" = ""USB2 World Facing Camera""
450 register "type" = "UPC_TYPE_INTERNAL"
451 device ref usb2_port7 on end
452 end
453 chip drivers/usb/acpi
454 register "desc" = ""USB2 Bluetooth""
455 register "type" = "UPC_TYPE_INTERNAL"
456 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
457 device ref usb2_port10 on end
458 end
459 chip drivers/usb/acpi
460 register "desc" = ""USB3 Type-A Port A0 (MLB)""
461 register "type" = "UPC_TYPE_USB3_A"
462 register "use_custom_pld" = "true"
463 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
464 device ref usb3_port1 on end
465 end
466 chip drivers/usb/acpi
467 register "desc" = ""USB3 WWAN""
468 register "type" = "UPC_TYPE_INTERNAL"
Dtrain Hsu764167b2023-05-18 17:34:56 +0800469 device ref usb3_port2 on
470 probe DB_LTE LTE_PRESENT
471 end
Van Chendea2c472023-03-21 09:34:18 +0800472 end
473 end
474 end
475 end
van_chene5fa3b12023-03-13 14:57:00 +0800476 end
van_chene5fa3b12023-03-13 14:57:00 +0800477end