Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | // Use simple device model for this file even in ramstage |
| 4 | #define __SIMPLE_DEVICE__ |
| 5 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 6 | #include <arch/romstage.h> |
| 7 | #include <cbmem.h> |
| 8 | #include <cpu/x86/mtrr.h> |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 10 | #include <program_loading.h> |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 11 | #include <stdint.h> |
| 12 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 13 | #include "e7505.h" |
| 14 | |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 15 | uintptr_t cbmem_top_chipset(void) |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 16 | { |
| 17 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 18 | uintptr_t tolm; |
| 19 | |
| 20 | /* This is at 128 MiB boundary. */ |
| 21 | tolm = pci_read_config16(mch, TOLM) >> 11; |
| 22 | tolm <<= 27; |
| 23 | |
Elyes Haouas | 799c321 | 2022-11-09 14:00:44 +0100 | [diff] [blame] | 24 | return tolm; |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | void northbridge_write_smram(u8 smram); |
| 28 | |
| 29 | void northbridge_write_smram(u8 smram) |
| 30 | { |
| 31 | const pci_devfn_t mch = PCI_DEV(0, 0, 0); |
| 32 | pci_write_config8(mch, SMRAMC, smram); |
| 33 | } |
| 34 | |
| 35 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 36 | { |
| 37 | uintptr_t top_of_ram; |
| 38 | |
| 39 | /* |
| 40 | * Choose to NOT set ROM as WP cacheable here. |
| 41 | * Timestamps indicate the CPU this northbridge code is |
| 42 | * connected to, performs better for memcpy() and un-lzma |
| 43 | * operations when source is left as UC. |
| 44 | */ |
| 45 | |
| 46 | pcf->skip_common_mtrr = 1; |
| 47 | |
| 48 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 49 | postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 50 | |
| 51 | /* Cache CBMEM region as WB. */ |
| 52 | top_of_ram = (uintptr_t)cbmem_top(); |
| 53 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, |
| 54 | MTRR_TYPE_WRBACK); |
| 55 | } |