Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 6 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 7 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 10 | #include <northbridge/intel/sandybridge/chip.h> |
| 11 | #include <device/pci_def.h> |
| 12 | #include <delay.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 13 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 17 | #include "sandybridge.h" |
| 18 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | /* FIXME: no ECC support */ |
| 20 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 21 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 22 | /* length: [1..4] */ |
| 23 | #define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 24 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 25 | static void sfence(void) |
| 26 | { |
| 27 | asm volatile ("sfence"); |
| 28 | } |
| 29 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 30 | /* Toggle IO reset bit */ |
| 31 | static void toggle_io_reset(void) |
| 32 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 33 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 34 | MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 35 | udelay(1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 36 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 37 | udelay(1); |
| 38 | } |
| 39 | |
| 40 | static u32 get_XOVER_CLK(u8 rankmap) |
| 41 | { |
| 42 | return rankmap << 24; |
| 43 | } |
| 44 | |
| 45 | static u32 get_XOVER_CMD(u8 rankmap) |
| 46 | { |
| 47 | u32 reg; |
| 48 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 49 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 50 | reg = 0x4000; |
| 51 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 52 | /* Enable xover ctl */ |
| 53 | if (rankmap & 0x03) |
| 54 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 55 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 56 | if (rankmap & 0x0c) |
| 57 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 58 | |
| 59 | return reg; |
| 60 | } |
| 61 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 62 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 63 | u8 get_CWL(u32 tCK) |
| 64 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 65 | /* Get CWL based on tCK using the following rule */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 66 | switch (tCK) { |
| 67 | case TCK_1333MHZ: |
| 68 | return 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 69 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 70 | case TCK_1200MHZ: |
| 71 | case TCK_1100MHZ: |
| 72 | return 11; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 73 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 74 | case TCK_1066MHZ: |
| 75 | case TCK_1000MHZ: |
| 76 | return 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 77 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 78 | case TCK_933MHZ: |
| 79 | case TCK_900MHZ: |
| 80 | return 9; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 81 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 82 | case TCK_800MHZ: |
| 83 | case TCK_700MHZ: |
| 84 | return 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 85 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 86 | case TCK_666MHZ: |
| 87 | return 7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 88 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 89 | case TCK_533MHZ: |
| 90 | return 6; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 91 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 92 | default: |
| 93 | return 5; |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | void dram_find_common_params(ramctr_timing *ctrl) |
| 98 | { |
| 99 | size_t valid_dimms; |
| 100 | int channel, slot; |
| 101 | dimm_info *dimms = &ctrl->info; |
| 102 | |
| 103 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 104 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 105 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 106 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 107 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 108 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 109 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 110 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 111 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 112 | valid_dimms++; |
| 113 | |
| 114 | /* Find all possible CAS combinations */ |
| 115 | ctrl->cas_supported &= dimm->cas_supported; |
| 116 | |
| 117 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 118 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 119 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 120 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 121 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 122 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 123 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 124 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 125 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 126 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 127 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 128 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 129 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 130 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 134 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 135 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 136 | if (!valid_dimms) |
| 137 | die("No valid DIMMs found"); |
| 138 | } |
| 139 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 140 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 141 | { |
| 142 | u32 reg; |
| 143 | int channel; |
| 144 | |
| 145 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 146 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 147 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 148 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 149 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 150 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 151 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 152 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 153 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 154 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 155 | } |
| 156 | } |
| 157 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 158 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 159 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 160 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 161 | |
| 162 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 163 | /* |
| 164 | * ODT stretch: |
| 165 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 166 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 167 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 168 | if (stretch == 2) |
| 169 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 170 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 171 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 172 | MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); |
| 173 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 174 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 175 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 176 | MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 177 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 178 | } |
| 179 | } |
| 180 | |
| 181 | void dram_timing_regs(ramctr_timing *ctrl) |
| 182 | { |
| 183 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 184 | int channel; |
| 185 | |
| 186 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 187 | /* BIN parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 188 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 189 | reg |= (ctrl->tRCD << 0); |
| 190 | reg |= (ctrl->tRP << 4); |
| 191 | reg |= (ctrl->CAS << 8); |
| 192 | reg |= (ctrl->CWL << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 193 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 194 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 195 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 196 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 197 | /* Regular access parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 198 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 199 | reg |= (ctrl->tRRD << 0); |
| 200 | reg |= (ctrl->tRTP << 4); |
| 201 | reg |= (ctrl->tCKE << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 202 | reg |= (ctrl->tWTR << 12); |
| 203 | reg |= (ctrl->tFAW << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 204 | reg |= (ctrl->tWR << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 205 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 206 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 207 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 208 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 209 | /* Other parameters */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 210 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 211 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 212 | reg |= (ctrl->tXPDLL << 0); |
| 213 | reg |= (ctrl->tXP << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 214 | reg |= (ctrl->tAONPD << 8); |
| 215 | reg |= 0xa0000; |
| 216 | printram("OTHP [%x] = %x\n", addr, reg); |
| 217 | MCHBAR32(addr) = reg; |
| 218 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 219 | /* FIXME: This register might as well not exist */ |
Angel Pons | 1aba2a3 | 2020-01-05 22:31:41 +0100 | [diff] [blame] | 220 | MCHBAR32(0x4014 + channel * 0x400) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 221 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 222 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 223 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 224 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 225 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 226 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 227 | * TC-Refresh timing parameters: |
| 228 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 229 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 230 | */ |
| 231 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 232 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 234 | ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); |
| 235 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 236 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 237 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 238 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 239 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 240 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 241 | /* Self-refresh timing parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 242 | reg = 0; |
| 243 | val32 = tDLLK; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 244 | reg = (reg & ~0x00000fff) | (val32 << 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 245 | val32 = ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 246 | reg = (reg & ~0x0000f000) | (val32 << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 247 | val32 = tDLLK - ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 248 | reg = (reg & ~0x03ff0000) | (val32 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 249 | val32 = ctrl->tMOD - 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 250 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 251 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 252 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 253 | } |
| 254 | } |
| 255 | |
| 256 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 257 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 258 | int channel; |
| 259 | dimm_info *info = &ctrl->info; |
| 260 | |
| 261 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 262 | dimm_attr *dimmA, *dimmB; |
| 263 | u32 reg = 0; |
| 264 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 265 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 266 | dimmA = &info->dimm[channel][0]; |
| 267 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 268 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 269 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 270 | dimmA = &info->dimm[channel][1]; |
| 271 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 272 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 273 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 274 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 275 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 276 | reg |= (dimmA->size_mb / 256) << 0; |
| 277 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 278 | reg |= (dimmA->width / 8 - 1) << 19; |
| 279 | } |
| 280 | |
| 281 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 282 | reg |= (dimmB->size_mb / 256) << 8; |
| 283 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 284 | reg |= (dimmB->width / 8 - 1) << 20; |
| 285 | } |
| 286 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 287 | reg |= 1 << 21; /* Rank interleave */ |
| 288 | reg |= 1 << 22; /* Enhanced interleave */ |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 289 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 290 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 291 | ctrl->mad_dimm[channel] = reg; |
| 292 | } else { |
| 293 | ctrl->mad_dimm[channel] = 0; |
| 294 | } |
| 295 | } |
| 296 | } |
| 297 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 298 | void dram_dimm_set_mapping(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 299 | { |
| 300 | int channel; |
| 301 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 302 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 303 | } |
| 304 | } |
| 305 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 306 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 307 | { |
| 308 | u32 reg, ch0size, ch1size; |
| 309 | u8 val; |
| 310 | reg = 0; |
| 311 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 312 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 313 | if (training) { |
| 314 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 315 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 316 | } else { |
| 317 | ch0size = ctrl->channel_size_mb[0]; |
| 318 | ch1size = ctrl->channel_size_mb[1]; |
| 319 | } |
| 320 | |
| 321 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 322 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 323 | val = ch1size / 256; |
| 324 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 325 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 326 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 327 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 328 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 329 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 330 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 331 | val = ch0size / 256; |
| 332 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 333 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 334 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 335 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 336 | } |
| 337 | } |
| 338 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 339 | #define DEFAULT_TCK TCK_800MHZ |
| 340 | |
| 341 | unsigned int get_mem_min_tck(void) |
| 342 | { |
| 343 | u32 reg32; |
| 344 | u8 rev; |
| 345 | const struct device *dev; |
| 346 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 347 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 348 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 349 | if (dev) |
| 350 | cfg = dev->chip_info; |
| 351 | |
| 352 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 353 | if (!cfg || cfg->max_mem_clock_mhz == 0) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 354 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 355 | if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
Patrick Rudolph | b794a69 | 2017-08-08 13:13:51 +0200 | [diff] [blame] | 356 | return TCK_1333MHZ; |
| 357 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 358 | rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 359 | |
| 360 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 361 | /* Read Capabilities A Register DMFC bits */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 362 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 363 | reg32 &= 0x7; |
| 364 | |
| 365 | switch (reg32) { |
| 366 | case 7: return TCK_533MHZ; |
| 367 | case 6: return TCK_666MHZ; |
| 368 | case 5: return TCK_800MHZ; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 369 | /* Reserved */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 370 | default: |
| 371 | break; |
| 372 | } |
| 373 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 374 | /* Read Capabilities B Register DMFC bits */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 375 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 376 | reg32 = (reg32 >> 4) & 0x7; |
| 377 | |
| 378 | switch (reg32) { |
| 379 | case 7: return TCK_533MHZ; |
| 380 | case 6: return TCK_666MHZ; |
| 381 | case 5: return TCK_800MHZ; |
| 382 | case 4: return TCK_933MHZ; |
| 383 | case 3: return TCK_1066MHZ; |
| 384 | case 2: return TCK_1200MHZ; |
| 385 | case 1: return TCK_1333MHZ; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 386 | /* Reserved */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 387 | default: |
| 388 | break; |
| 389 | } |
| 390 | } |
| 391 | return DEFAULT_TCK; |
| 392 | } else { |
| 393 | if (cfg->max_mem_clock_mhz >= 1066) |
| 394 | return TCK_1066MHZ; |
| 395 | else if (cfg->max_mem_clock_mhz >= 933) |
| 396 | return TCK_933MHZ; |
| 397 | else if (cfg->max_mem_clock_mhz >= 800) |
| 398 | return TCK_800MHZ; |
| 399 | else if (cfg->max_mem_clock_mhz >= 666) |
| 400 | return TCK_666MHZ; |
| 401 | else if (cfg->max_mem_clock_mhz >= 533) |
| 402 | return TCK_533MHZ; |
| 403 | else |
| 404 | return TCK_400MHZ; |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 409 | |
| 410 | static unsigned int get_mmio_size(void) |
| 411 | { |
| 412 | const struct device *dev; |
| 413 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 414 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 415 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 416 | if (dev) |
| 417 | cfg = dev->chip_info; |
| 418 | |
| 419 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 420 | if (!cfg || cfg->pci_mmio_size == 0) |
| 421 | return DEFAULT_PCI_MMIO_SIZE; |
| 422 | else |
| 423 | return cfg->pci_mmio_size; |
| 424 | } |
| 425 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 426 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 427 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 428 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 429 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 430 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 431 | uint16_t ggc; |
| 432 | |
| 433 | mmiosize = get_mmio_size(); |
| 434 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 435 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 436 | if (!(ggc & 2)) { |
| 437 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 438 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 439 | } else { |
| 440 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 441 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 442 | } |
| 443 | |
| 444 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 445 | |
| 446 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 447 | |
| 448 | mestolenbase = tom - me_uma_size; |
| 449 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 450 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 451 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 452 | gfxstolenbase = toludbase - gfxstolen; |
| 453 | gttbase = gfxstolenbase - gttsize; |
| 454 | |
| 455 | tsegbase = gttbase - tsegsize; |
| 456 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 457 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 458 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 459 | tsegbase &= ~(tsegsize - 1); |
| 460 | |
| 461 | gttbase -= tsegbasedelta; |
| 462 | gfxstolenbase -= tsegbasedelta; |
| 463 | toludbase -= tsegbasedelta; |
| 464 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 465 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 466 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 467 | /* Reclaim is possible */ |
| 468 | reclaim = 1; |
| 469 | remapbase = MAX(4096, tom - me_uma_size); |
| 470 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 471 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 472 | } else { |
| 473 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 474 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 475 | touudbase = tom - me_uma_size; |
| 476 | } |
| 477 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 478 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 479 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 480 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 481 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 482 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 483 | val = tom & 0xfff; |
| 484 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 485 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 486 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 487 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 488 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 489 | val = tom & 0xfffff000; |
| 490 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 491 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 492 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 493 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 494 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 495 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 496 | val = toludbase & 0xfff; |
| 497 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 498 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 499 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 500 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 501 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 502 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 503 | val = touudbase & 0xfff; |
| 504 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 505 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 506 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 507 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 508 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 509 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 510 | val = touudbase & 0xfffff000; |
| 511 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 512 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 513 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 514 | |
| 515 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 516 | /* REMAP BASE */ |
| 517 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 518 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 519 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 520 | /* REMAP LIMIT */ |
| 521 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 522 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 523 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 524 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 525 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 526 | val = tsegbase & 0xfff; |
| 527 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 528 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 529 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 530 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 531 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 532 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 533 | val = gfxstolenbase & 0xfff; |
| 534 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 535 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 536 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 537 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 538 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 539 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 540 | val = gttbase & 0xfff; |
| 541 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 542 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 543 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 544 | |
| 545 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 546 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 547 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 548 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 549 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 550 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 551 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 552 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 553 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 554 | val = mestolenbase & 0xfff; |
| 555 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 556 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 557 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 558 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 559 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 560 | val = mestolenbase & 0xfffff000; |
| 561 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 562 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 563 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 564 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 565 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 566 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 567 | val = (0x80000 - me_uma_size) & 0xfff; |
| 568 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 569 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 570 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 571 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 572 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 573 | } |
| 574 | } |
| 575 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 576 | static void wait_for_iosav(int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 577 | { |
| 578 | while (1) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 579 | if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 580 | return; |
| 581 | } |
| 582 | } |
| 583 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 584 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 585 | { |
| 586 | int channel, slotrank; |
| 587 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 588 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 589 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 590 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 591 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 592 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 593 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 594 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 595 | |
| 596 | /* DRAM command ZQCS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 597 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 598 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x80c01; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 599 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 600 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 601 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 602 | /* |
| 603 | * Execute command queue - why is bit 22 set here?! |
| 604 | * |
| 605 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 606 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 607 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 608 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 609 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 610 | } |
| 611 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 612 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 613 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 614 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 615 | int channel; |
| 616 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 617 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 618 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 619 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 620 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 621 | } while ((reg & 0x14) == 0); |
| 622 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 623 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 624 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 625 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 626 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 627 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 628 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 629 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 630 | /* Assert DIMM reset signal */ |
| 631 | MCHBAR32_AND(MC_INIT_STATE_G, ~2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 632 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 633 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 634 | udelay(200); |
| 635 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 636 | /* Deassert DIMM reset signal */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 637 | MCHBAR32_OR(MC_INIT_STATE_G, 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 638 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 639 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 640 | udelay(500); |
| 641 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 642 | /* Enable DCLK */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 643 | MCHBAR32_OR(MC_INIT_STATE_G, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 644 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 645 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 646 | udelay(1); |
| 647 | |
| 648 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 649 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 650 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 651 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 652 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 653 | /* Wait 10ns for ranks to settle */ |
| 654 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 655 | |
| 656 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 657 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 658 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 659 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 660 | write_reset(ctrl); |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 665 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 666 | /* Get ODT based on rankmap */ |
| 667 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 668 | |
| 669 | if (dimms_per_ch == 1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 670 | return (const odtmap){60, 60}; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 671 | } else { |
| 672 | return (const odtmap){120, 30}; |
| 673 | } |
| 674 | } |
| 675 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 676 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 677 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 678 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 679 | |
| 680 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 681 | /* DDR3 Rank1 Address mirror |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 682 | swap the following pins: |
| 683 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 684 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 685 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | /* DRAM command MRS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 689 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f000; |
| 690 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 691 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 692 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 693 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 694 | |
| 695 | /* DRAM command MRS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 696 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f000; |
| 697 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 698 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 699 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 700 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 701 | |
| 702 | /* DRAM command MRS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 703 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0f000; |
| 704 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 705 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 706 | (slotrank << 24) | (reg << 20) | val | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 707 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 708 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 709 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 710 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 711 | } |
| 712 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 713 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 714 | { |
| 715 | u16 mr0reg, mch_cas, mch_wr; |
| 716 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 717 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 718 | |
| 719 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 720 | mr0reg = 0x100; |
| 721 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 722 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 723 | if (ctrl->CAS < 12) { |
| 724 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 725 | } else { |
| 726 | mch_cas = (u16) (ctrl->CAS - 12); |
| 727 | mch_cas = ((mch_cas << 1) | 0x1); |
| 728 | } |
| 729 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 730 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 731 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 732 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 733 | mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); |
| 734 | mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); |
| 735 | mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 736 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 737 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
| 738 | mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 739 | return mr0reg; |
| 740 | } |
| 741 | |
| 742 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 743 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 744 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | static u32 encode_odt(u32 odt) |
| 748 | { |
| 749 | switch (odt) { |
| 750 | case 30: |
| 751 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 752 | case 60: |
| 753 | return (1 << 2); // RZQ/4 |
| 754 | case 120: |
| 755 | return (1 << 6); // RZQ/2 |
| 756 | default: |
| 757 | case 0: |
| 758 | return 0; |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 763 | { |
| 764 | odtmap odt; |
| 765 | u32 mr1reg; |
| 766 | |
| 767 | odt = get_ODT(ctrl, rank, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 768 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 769 | |
| 770 | mr1reg |= encode_odt(odt.rttnom); |
| 771 | |
| 772 | return mr1reg; |
| 773 | } |
| 774 | |
| 775 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 776 | { |
| 777 | u16 mr1reg; |
| 778 | |
| 779 | mr1reg = make_mr1(ctrl, rank, channel); |
| 780 | |
| 781 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 782 | } |
| 783 | |
| 784 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 785 | { |
| 786 | u16 pasr, cwl, mr2reg; |
| 787 | odtmap odt; |
| 788 | int srt; |
| 789 | |
| 790 | pasr = 0; |
| 791 | cwl = ctrl->CWL - 5; |
| 792 | odt = get_ODT(ctrl, rank, channel); |
| 793 | |
| 794 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 795 | |
| 796 | mr2reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 797 | mr2reg = (mr2reg & ~0x07) | pasr; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 798 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 799 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 800 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 801 | mr2reg |= (odt.rttwr / 60) << 9; |
| 802 | |
| 803 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 804 | } |
| 805 | |
| 806 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 807 | { |
| 808 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 809 | } |
| 810 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 811 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 812 | { |
| 813 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 814 | int channel; |
| 815 | |
| 816 | FOR_ALL_POPULATED_CHANNELS { |
| 817 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 818 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 819 | dram_mr2(ctrl, slotrank, channel); |
| 820 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 821 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 822 | dram_mr3(ctrl, slotrank, channel); |
| 823 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 824 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 825 | dram_mr1(ctrl, slotrank, channel); |
| 826 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 827 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 828 | dram_mr0(ctrl, slotrank, channel); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 833 | MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = 0x7; |
| 834 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 835 | MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 836 | MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 837 | |
| 838 | /* DRAM command ZQCL */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 839 | MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = 0x1f003; |
| 840 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 841 | MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 842 | MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 843 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 844 | /* Execute command queue on all channels. Do it four times. */ |
| 845 | MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 846 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 847 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 848 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 849 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 850 | } |
| 851 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 852 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 853 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 854 | |
| 855 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 856 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 857 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 858 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 859 | |
| 860 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 861 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 862 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 863 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 864 | |
| 865 | /* DRAM command ZQCS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 866 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 867 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; |
| 868 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 869 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 870 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 871 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 872 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 873 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 874 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 875 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 876 | } |
| 877 | } |
| 878 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 879 | static const u32 lane_base[] = { |
| 880 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 881 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 882 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 883 | }; |
| 884 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 885 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 886 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 887 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 888 | int lane; |
| 889 | int slotrank, slot; |
| 890 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 891 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 892 | |
| 893 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 894 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 895 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 896 | } |
| 897 | |
| 898 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 899 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 900 | case 0: |
| 901 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 902 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 903 | break; |
| 904 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 905 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 906 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 907 | break; |
| 908 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 909 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 910 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 911 | break; |
| 912 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 913 | pi_coding_ctrl[slot] = |
| 914 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 915 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 916 | break; |
| 917 | } |
| 918 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 919 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 920 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 921 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 922 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 923 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 924 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 925 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 926 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 927 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 928 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 929 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 930 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 931 | |
| 932 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 933 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 934 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 935 | if (shift < 0) |
| 936 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 937 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 938 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 939 | |
| 940 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 941 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 942 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 943 | } |
| 944 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 945 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 946 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 947 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 948 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 949 | reg_io_latency &= 0xffff0000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 950 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 951 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 952 | |
| 953 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 954 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 955 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 956 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 957 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 958 | |
| 959 | if (shift < 0) |
| 960 | shift = 0; |
| 961 | |
| 962 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 963 | post_timA_min_high = MIN(post_timA_min_high, |
| 964 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 965 | timA + shift) >> 6); |
| 966 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 967 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 968 | timA >> 6); |
| 969 | post_timA_max_high = MAX(post_timA_max_high, |
| 970 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 971 | timA + shift) >> 6); |
| 972 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 973 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 974 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 975 | } |
| 976 | |
| 977 | if (pre_timA_max_high - pre_timA_min_high < |
| 978 | post_timA_max_high - post_timA_min_high) |
| 979 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 980 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 981 | else if (pre_timA_max_high - pre_timA_min_high > |
| 982 | post_timA_max_high - post_timA_min_high) |
| 983 | shift_402x = -1; |
| 984 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 985 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 986 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 987 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 988 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 989 | reg_roundtrip_latency |= |
| 990 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 991 | shift_402x) << (8 * slotrank); |
| 992 | |
| 993 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 994 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 995 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 996 | timA + shift) & 0x3f) |
| 997 | | |
| 998 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 999 | rising + shift) << 8) |
| 1000 | | |
| 1001 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1002 | timA + shift - |
| 1003 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1004 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1005 | falling + shift) << 20)); |
| 1006 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1007 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1008 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1009 | timC + shift) & 0x3f) |
| 1010 | | |
| 1011 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1012 | timB + shift) & 0x3f) << 8) |
| 1013 | | |
| 1014 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1015 | timB + shift) & 0x1c0) << 9) |
| 1016 | | |
| 1017 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1018 | timC + shift) & 0x40) << 13)); |
| 1019 | } |
| 1020 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1021 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1022 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1023 | } |
| 1024 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1025 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1026 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1027 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1028 | |
| 1029 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1030 | write MR3 MPR enable |
| 1031 | in this mode only RD and RDA are allowed |
| 1032 | all reads return a predefined pattern */ |
| 1033 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 1034 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = (0xc01 | (ctrl->tMOD << 16)); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1035 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1036 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1037 | |
| 1038 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1039 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 1040 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4040c01; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1041 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1042 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1043 | |
| 1044 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1045 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 1046 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x100f | ((ctrl->CAS + 36) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1047 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1048 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1049 | |
| 1050 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1051 | write MR3 MPR disable */ |
| 1052 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 1053 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1054 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1055 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1056 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1057 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1058 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1059 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1060 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1061 | } |
| 1062 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1063 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1064 | { |
| 1065 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1066 | |
| 1067 | return (MCHBAR32(lane_base[lane] + |
| 1068 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1069 | } |
| 1070 | |
| 1071 | struct run { |
| 1072 | int middle; |
| 1073 | int end; |
| 1074 | int start; |
| 1075 | int all; |
| 1076 | int length; |
| 1077 | }; |
| 1078 | |
| 1079 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1080 | { |
| 1081 | int i, ls; |
| 1082 | int bl = 0, bs = 0; |
| 1083 | struct run ret; |
| 1084 | |
| 1085 | ls = 0; |
| 1086 | for (i = 0; i < 2 * sz; i++) |
| 1087 | if (seq[i % sz]) { |
| 1088 | if (i - ls > bl) { |
| 1089 | bl = i - ls; |
| 1090 | bs = ls; |
| 1091 | } |
| 1092 | ls = i + 1; |
| 1093 | } |
| 1094 | if (bl == 0) { |
| 1095 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1096 | ret.start = 0; |
| 1097 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1098 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1099 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1100 | return ret; |
| 1101 | } |
| 1102 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1103 | ret.start = bs % sz; |
| 1104 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1105 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1106 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1107 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1108 | |
| 1109 | return ret; |
| 1110 | } |
| 1111 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1112 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1113 | { |
| 1114 | int timA; |
| 1115 | int statistics[NUM_LANES][128]; |
| 1116 | int lane; |
| 1117 | |
| 1118 | for (timA = 0; timA < 128; timA++) { |
| 1119 | FOR_ALL_LANES { |
| 1120 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1121 | } |
| 1122 | program_timings(ctrl, channel); |
| 1123 | |
| 1124 | test_timA(ctrl, channel, slotrank); |
| 1125 | |
| 1126 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1127 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1128 | } |
| 1129 | } |
| 1130 | FOR_ALL_LANES { |
| 1131 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1132 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1133 | upperA[lane] = rn.end; |
| 1134 | if (upperA[lane] < rn.middle) |
| 1135 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1136 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1137 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1138 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1139 | } |
| 1140 | } |
| 1141 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1142 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1143 | { |
| 1144 | int timA_delta; |
| 1145 | int statistics[NUM_LANES][51]; |
| 1146 | int lane, i; |
| 1147 | |
| 1148 | memset(statistics, 0, sizeof(statistics)); |
| 1149 | |
| 1150 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1151 | |
| 1152 | FOR_ALL_LANES { |
| 1153 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1154 | = upperA[lane] + timA_delta + 0x40; |
| 1155 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1156 | program_timings(ctrl, channel); |
| 1157 | |
| 1158 | for (i = 0; i < 100; i++) { |
| 1159 | test_timA(ctrl, channel, slotrank); |
| 1160 | FOR_ALL_LANES { |
| 1161 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1162 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1163 | } |
| 1164 | } |
| 1165 | } |
| 1166 | FOR_ALL_LANES { |
| 1167 | int last_zero, first_all; |
| 1168 | |
| 1169 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1170 | if (statistics[lane][last_zero + 25]) |
| 1171 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1172 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1173 | last_zero--; |
| 1174 | for (first_all = -25; first_all <= 25; first_all++) |
| 1175 | if (statistics[lane][first_all + 25] == 100) |
| 1176 | break; |
| 1177 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1178 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1179 | |
| 1180 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1181 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1182 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1183 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1184 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1185 | } |
| 1186 | } |
| 1187 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1188 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1189 | { |
| 1190 | int works[NUM_LANES]; |
| 1191 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1192 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1193 | while (1) { |
| 1194 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1195 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1196 | program_timings(ctrl, channel); |
| 1197 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1198 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1199 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1200 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1201 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1202 | if (works[lane]) |
| 1203 | some_works = 1; |
| 1204 | else |
| 1205 | all_works = 0; |
| 1206 | } |
| 1207 | if (all_works) |
| 1208 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1209 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1210 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1211 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1212 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1213 | channel, slotrank); |
| 1214 | return MAKE_ERR; |
| 1215 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1216 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1217 | printram("4024 -= 2;\n"); |
| 1218 | continue; |
| 1219 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1220 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1221 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1222 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1223 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1224 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1225 | channel, slotrank); |
| 1226 | return MAKE_ERR; |
| 1227 | } |
| 1228 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1229 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1230 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1231 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1232 | } |
| 1233 | } |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
| 1237 | struct timA_minmax { |
| 1238 | int timA_min_high, timA_max_high; |
| 1239 | }; |
| 1240 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1241 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1242 | struct timA_minmax *mnmx) |
| 1243 | { |
| 1244 | int lane; |
| 1245 | mnmx->timA_min_high = 7; |
| 1246 | mnmx->timA_max_high = 0; |
| 1247 | |
| 1248 | FOR_ALL_LANES { |
| 1249 | if (mnmx->timA_min_high > |
| 1250 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1251 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1252 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1253 | if (mnmx->timA_max_high < |
| 1254 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1255 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1256 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1257 | } |
| 1258 | } |
| 1259 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1260 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1261 | struct timA_minmax *mnmx) |
| 1262 | { |
| 1263 | struct timA_minmax post; |
| 1264 | int shift_402x = 0; |
| 1265 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1266 | /* Get changed maxima */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1267 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1268 | |
| 1269 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1270 | post.timA_max_high - post.timA_min_high) |
| 1271 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1272 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1273 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1274 | post.timA_max_high - post.timA_min_high) |
| 1275 | shift_402x = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1276 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1277 | else |
| 1278 | shift_402x = 0; |
| 1279 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1280 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1281 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1282 | printram("4024 += %d;\n", shift_402x); |
| 1283 | printram("4028 += %d;\n", shift_402x); |
| 1284 | } |
| 1285 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1286 | /* |
| 1287 | * Compensate the skew between DQS and DQs. |
| 1288 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1289 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1290 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1291 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1292 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1293 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1294 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1295 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1296 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1297 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1298 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1299 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1300 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1301 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1302 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1303 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1304 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1305 | { |
| 1306 | int channel, slotrank, lane; |
| 1307 | int err; |
| 1308 | |
| 1309 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1310 | int all_high, some_high; |
| 1311 | int upperA[NUM_LANES]; |
| 1312 | struct timA_minmax mnmx; |
| 1313 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1314 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1315 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1316 | /* DRAM command PREA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1317 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; |
| 1318 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1319 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1320 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1321 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1322 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1323 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1324 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1325 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1326 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1327 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1328 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1329 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1330 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1331 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1332 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1333 | all_high = 1; |
| 1334 | some_high = 0; |
| 1335 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1336 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1337 | some_high = 1; |
| 1338 | else |
| 1339 | all_high = 0; |
| 1340 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1341 | |
| 1342 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1343 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1344 | printram("4028--;\n"); |
| 1345 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1346 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1347 | upperA[lane] -= 0x40; |
| 1348 | |
| 1349 | } |
| 1350 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1351 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1352 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1353 | printram("4024++;\n"); |
| 1354 | printram("4028++;\n"); |
| 1355 | } |
| 1356 | |
| 1357 | program_timings(ctrl, channel); |
| 1358 | |
| 1359 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1360 | |
| 1361 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1362 | if (err) |
| 1363 | return err; |
| 1364 | |
| 1365 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1366 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1367 | |
| 1368 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1369 | |
| 1370 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1371 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1372 | |
| 1373 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1374 | ctrl->timings[channel][slotrank].lanes[lane].timA -= |
| 1375 | mnmx.timA_min_high * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1376 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1377 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1378 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1379 | |
| 1380 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1381 | |
| 1382 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1383 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1384 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1385 | |
| 1386 | printram("final results:\n"); |
| 1387 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1388 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1389 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1390 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1391 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1392 | |
| 1393 | toggle_io_reset(); |
| 1394 | } |
| 1395 | |
| 1396 | FOR_ALL_POPULATED_CHANNELS { |
| 1397 | program_timings(ctrl, channel); |
| 1398 | } |
| 1399 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1400 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1401 | } |
| 1402 | return 0; |
| 1403 | } |
| 1404 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1405 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1406 | { |
| 1407 | int lane; |
| 1408 | |
| 1409 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1410 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1411 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1412 | } |
| 1413 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1414 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1415 | |
| 1416 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1417 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; |
| 1418 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
| 1419 | (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1420 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | (6 << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1421 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1422 | |
| 1423 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1424 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; |
| 1425 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8041001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1426 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1427 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1428 | |
| 1429 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1430 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; |
| 1431 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x80411f4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1432 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1433 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1434 | |
| 1435 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1436 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; |
| 1437 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
| 1438 | 0x08000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1439 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1440 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1441 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1442 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1443 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1444 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1445 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1446 | |
| 1447 | /* DRAM command PREA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1448 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; |
| 1449 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1450 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1451 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1452 | |
| 1453 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1454 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; |
| 1455 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = |
| 1456 | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1457 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1458 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1459 | |
| 1460 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1461 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 1462 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 1463 | 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1464 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1465 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1466 | |
| 1467 | /* DRAM command PREA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1468 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; |
| 1469 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1470 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1471 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1472 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1473 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1474 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1475 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1476 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1477 | } |
| 1478 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1479 | static void timC_threshold_process(int *data, const int count) |
| 1480 | { |
| 1481 | int min = data[0]; |
| 1482 | int max = min; |
| 1483 | int i; |
| 1484 | for (i = 1; i < count; i++) { |
| 1485 | if (min > data[i]) |
| 1486 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1487 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1488 | if (max < data[i]) |
| 1489 | max = data[i]; |
| 1490 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1491 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1492 | for (i = 0; i < count; i++) |
| 1493 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1494 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1495 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1496 | } |
| 1497 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1498 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1499 | { |
| 1500 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1501 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1502 | int lane; |
| 1503 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1504 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1505 | |
| 1506 | /* DRAM command PREA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1507 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; |
| 1508 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1509 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1510 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1511 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1512 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1513 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1514 | |
| 1515 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1516 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1517 | program_timings(ctrl, channel); |
| 1518 | |
| 1519 | test_timC(ctrl, channel, slotrank); |
| 1520 | |
| 1521 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1522 | stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1523 | } |
| 1524 | } |
| 1525 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1526 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1527 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1528 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1529 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1530 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1531 | /* |
| 1532 | * With command training not being done yet, the lane can be erroneous. |
| 1533 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1534 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1535 | timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1536 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1537 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1538 | if (rn.all || rn.length < 8) { |
| 1539 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1540 | return MAKE_ERR; |
| 1541 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1542 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1543 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1544 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1545 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1546 | } |
| 1547 | return 0; |
| 1548 | } |
| 1549 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1550 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1551 | { |
| 1552 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1553 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1554 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1555 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1556 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1557 | return ret; |
| 1558 | } |
| 1559 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1560 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1561 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1562 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1563 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1564 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1565 | for (j = 0; j < 16; j++) |
| 1566 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1567 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1568 | sfence(); |
| 1569 | } |
| 1570 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1571 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1572 | { |
| 1573 | int ret = 0; |
| 1574 | int channel; |
| 1575 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1576 | return ret; |
| 1577 | } |
| 1578 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1579 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1580 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1581 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1582 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1583 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1584 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1585 | for (j = 0; j < 16; j++) |
| 1586 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1587 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1588 | for (j = 0; j < 16; j++) |
| 1589 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1590 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1591 | sfence(); |
| 1592 | } |
| 1593 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1594 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1595 | { |
| 1596 | int channel, slotrank, lane; |
| 1597 | |
| 1598 | FOR_ALL_POPULATED_CHANNELS { |
| 1599 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1600 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1601 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1602 | } |
| 1603 | |
| 1604 | program_timings(ctrl, channel); |
| 1605 | |
| 1606 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1607 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1608 | |
| 1609 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1610 | write MR3 MPR enable |
| 1611 | in this mode only RD and RDA are allowed |
| 1612 | all reads return a predefined pattern */ |
| 1613 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 1614 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1615 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1616 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1617 | (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1618 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1619 | |
| 1620 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1621 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 1622 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 1623 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1624 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1625 | |
| 1626 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1627 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 1628 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1629 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1630 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1631 | (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1632 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1633 | |
| 1634 | /* DRAM command MRS |
| 1635 | * write MR3 MPR disable */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1636 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 1637 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1638 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1639 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1640 | (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1641 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1642 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1643 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1644 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1645 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1646 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1647 | } |
| 1648 | |
| 1649 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1650 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1651 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1652 | } |
| 1653 | |
| 1654 | program_timings(ctrl, channel); |
| 1655 | |
| 1656 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1657 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1658 | /* DRAM command MRS |
| 1659 | * write MR3 MPR enable |
| 1660 | * in this mode only RD and RDA are allowed |
| 1661 | * all reads return a predefined pattern */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1662 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 1663 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1664 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1665 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1666 | (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1667 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1668 | |
| 1669 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1670 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 1671 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 1672 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1673 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1674 | |
| 1675 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1676 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 1677 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1678 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1679 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1680 | (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1681 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1682 | |
| 1683 | /* DRAM command MRS |
| 1684 | * write MR3 MPR disable */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1685 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 1686 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1687 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1688 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1689 | (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1690 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1691 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1692 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1693 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1694 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1695 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1696 | } |
| 1697 | } |
| 1698 | } |
| 1699 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1700 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1701 | { |
| 1702 | /* enable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1703 | write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1704 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1705 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1706 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1707 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f207; |
| 1708 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1709 | 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1710 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 8 | (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1711 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1712 | |
| 1713 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1714 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f107; |
| 1715 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1716 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1717 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1718 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1719 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1720 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1721 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1722 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1723 | |
| 1724 | /* disable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1725 | write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1726 | } |
| 1727 | |
| 1728 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1729 | { |
| 1730 | int timB; |
| 1731 | int statistics[NUM_LANES][128]; |
| 1732 | int lane; |
| 1733 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1734 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1735 | |
| 1736 | for (timB = 0; timB < 128; timB++) { |
| 1737 | FOR_ALL_LANES { |
| 1738 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1739 | } |
| 1740 | program_timings(ctrl, channel); |
| 1741 | |
| 1742 | test_timB(ctrl, channel, slotrank); |
| 1743 | |
| 1744 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1745 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1746 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1747 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1748 | } |
| 1749 | } |
| 1750 | FOR_ALL_LANES { |
| 1751 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1752 | /* |
| 1753 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 1754 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 1755 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1756 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 1757 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1758 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1759 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 1760 | */ |
| 1761 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1762 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1763 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1764 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1765 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1766 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1767 | if (rn.all) { |
| 1768 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1769 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1770 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1771 | return MAKE_ERR; |
| 1772 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1773 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1774 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1775 | } |
| 1776 | return 0; |
| 1777 | } |
| 1778 | |
| 1779 | static int get_timB_high_adjust(u64 val) |
| 1780 | { |
| 1781 | int i; |
| 1782 | |
| 1783 | /* good */ |
| 1784 | if (val == 0xffffffffffffffffLL) |
| 1785 | return 0; |
| 1786 | |
| 1787 | if (val >= 0xf000000000000000LL) { |
| 1788 | /* needs negative adjustment */ |
| 1789 | for (i = 0; i < 8; i++) |
| 1790 | if (val << (8 * (7 - i) + 4)) |
| 1791 | return -i; |
| 1792 | } else { |
| 1793 | /* needs positive adjustment */ |
| 1794 | for (i = 0; i < 8; i++) |
| 1795 | if (val >> (8 * (7 - i) + 4)) |
| 1796 | return i; |
| 1797 | } |
| 1798 | return 8; |
| 1799 | } |
| 1800 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1801 | static void adjust_high_timB(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1802 | { |
| 1803 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1804 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1805 | FOR_ALL_POPULATED_CHANNELS { |
| 1806 | fill_pattern1(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1807 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1808 | } |
| 1809 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1810 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1811 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1812 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1813 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1814 | |
| 1815 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1816 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; |
| 1817 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tRCD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1818 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1819 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1820 | |
| 1821 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1822 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f207; |
| 1823 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8040c01; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1824 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1825 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1826 | |
| 1827 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1828 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f201; |
| 1829 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x8041003; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1830 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1831 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x3e2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1832 | |
| 1833 | /* DRAM command NOP */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1834 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f207; |
| 1835 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1836 | 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1837 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1838 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1839 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1840 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1841 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1842 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1843 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1844 | |
| 1845 | /* DRAM command PREA */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1846 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f002; |
| 1847 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1848 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1849 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1850 | |
| 1851 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1852 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f006; |
| 1853 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1854 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1855 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1856 | |
| 1857 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1858 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x3f105; |
| 1859 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x4000c01 | ((ctrl->tRP + |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1860 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1861 | ctrl->timings[channel][slotrank].io_latency) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1862 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60008; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1863 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1864 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1865 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1866 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1867 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1868 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1869 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1870 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1871 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1872 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1873 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1874 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1875 | get_timB_high_adjust(res) * 64; |
| 1876 | |
| 1877 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1878 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 1879 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1880 | } |
| 1881 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1882 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1883 | } |
| 1884 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1885 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1886 | { |
| 1887 | int slotrank; |
| 1888 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1889 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1890 | |
| 1891 | /* choose an existing rank. */ |
| 1892 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 1893 | |
| 1894 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1895 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 1896 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1897 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1898 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1899 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1900 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1901 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1902 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1903 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1904 | } |
| 1905 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1906 | /* |
| 1907 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1908 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1909 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 1910 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 1911 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 1912 | * CLK/ADDR/CMD signals have the same routing delay. |
| 1913 | * |
| 1914 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 1915 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 1916 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1917 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1918 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1919 | { |
| 1920 | int channel, slotrank, lane; |
| 1921 | int err; |
| 1922 | |
| 1923 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1924 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1925 | |
| 1926 | FOR_ALL_POPULATED_CHANNELS { |
| 1927 | write_op(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1928 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1929 | } |
| 1930 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1931 | /* Refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1932 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1933 | FOR_ALL_POPULATED_CHANNELS { |
| 1934 | write_op(ctrl, channel); |
| 1935 | } |
| 1936 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1937 | /* Enable write leveling on all ranks |
| 1938 | Disable all DQ outputs |
| 1939 | Only NOP is allowed in this mode */ |
| 1940 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 1941 | write_mrreg(ctrl, channel, slotrank, 1, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1942 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1943 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1944 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1945 | |
| 1946 | toggle_io_reset(); |
| 1947 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1948 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1949 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1950 | err = discover_timB(ctrl, channel, slotrank); |
| 1951 | if (err) |
| 1952 | return err; |
| 1953 | } |
| 1954 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1955 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1956 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1957 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1958 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1959 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1960 | |
| 1961 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1962 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1963 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1964 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1965 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1966 | |
| 1967 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1968 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); |
| 1969 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 1970 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1971 | |
| 1972 | /* DRAM command ZQCS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1973 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 1974 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x659001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1975 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1976 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1977 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1978 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1979 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1980 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1981 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | toggle_io_reset(); |
| 1985 | |
| 1986 | printram("CPE\n"); |
| 1987 | precharge(ctrl); |
| 1988 | printram("CPF\n"); |
| 1989 | |
| 1990 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1991 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1992 | } |
| 1993 | |
| 1994 | FOR_ALL_POPULATED_CHANNELS { |
| 1995 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1996 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1997 | } |
| 1998 | |
| 1999 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2000 | err = discover_timC(ctrl, channel, slotrank); |
| 2001 | if (err) |
| 2002 | return err; |
| 2003 | } |
| 2004 | |
| 2005 | FOR_ALL_POPULATED_CHANNELS |
| 2006 | program_timings(ctrl, channel); |
| 2007 | |
| 2008 | /* measure and adjust timB timings */ |
| 2009 | adjust_high_timB(ctrl); |
| 2010 | |
| 2011 | FOR_ALL_POPULATED_CHANNELS |
| 2012 | program_timings(ctrl, channel); |
| 2013 | |
| 2014 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2015 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2016 | } |
| 2017 | return 0; |
| 2018 | } |
| 2019 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2020 | static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2021 | { |
| 2022 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2023 | int timC_delta; |
| 2024 | int lanes_ok = 0; |
| 2025 | int ctr = 0; |
| 2026 | int lane; |
| 2027 | |
| 2028 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2029 | FOR_ALL_LANES { |
| 2030 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2031 | saved_rt.lanes[lane].timC + timC_delta; |
| 2032 | } |
| 2033 | program_timings(ctrl, channel); |
| 2034 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2035 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2036 | } |
| 2037 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2038 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2039 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2040 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2041 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2042 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; |
| 2043 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2044 | ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2045 | | 8 | (ctrl->tRCD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2046 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2047 | (slotrank << 24) | ctr | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2048 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x244; |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 2049 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2050 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2051 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; |
| 2052 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2053 | 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2054 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24); |
| 2055 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2056 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x20e42; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2057 | |
| 2058 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2059 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2060 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2061 | 0x4001020 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2062 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24); |
| 2063 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2064 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x20e42; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2065 | |
| 2066 | /* DRAM command PRE */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2067 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; |
| 2068 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xf1001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2069 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2070 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2071 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2072 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2073 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2074 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2075 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2076 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2077 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2078 | |
| 2079 | if (r32 == 0) |
| 2080 | lanes_ok |= 1 << lane; |
| 2081 | } |
| 2082 | ctr++; |
| 2083 | if (lanes_ok == ((1 << NUM_LANES) - 1)) |
| 2084 | break; |
| 2085 | } |
| 2086 | |
| 2087 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2088 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2089 | return lanes_ok != ((1 << NUM_LANES) - 1); |
| 2090 | } |
| 2091 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2092 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2093 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2094 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2095 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2096 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2097 | |
| 2098 | if (patno) { |
| 2099 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2100 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2101 | for (i = 0; i < 32; i++) { |
| 2102 | for (j = 0; j < 16; j++) { |
| 2103 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2104 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2105 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2106 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2107 | |
| 2108 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2109 | } |
| 2110 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2111 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2112 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2113 | for (j = 0; j < 16; j++) { |
| 2114 | const u32 val = pattern[i][j]; |
| 2115 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2116 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2117 | } |
| 2118 | sfence(); |
| 2119 | } |
| 2120 | } |
| 2121 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2122 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2123 | { |
| 2124 | int channel, slotrank; |
| 2125 | |
| 2126 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2127 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2128 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2129 | /* Choose an existing rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2130 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2131 | |
| 2132 | /* DRAM command ZQCS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2133 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 2134 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2135 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2136 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2137 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2138 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2139 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2140 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2141 | wait_for_iosav(channel); |
| 2142 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2143 | } |
| 2144 | |
| 2145 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2146 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2147 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2148 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2149 | |
| 2150 | /* choose an existing rank. */ |
| 2151 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2152 | |
| 2153 | /* DRAM command ZQCS */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2154 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0f003; |
| 2155 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2156 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2157 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x3e0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2158 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2159 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2160 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2161 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2162 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2163 | } |
| 2164 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2165 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2166 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2167 | |
| 2168 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2169 | dram_mrscommands(ctrl); |
| 2170 | |
| 2171 | toggle_io_reset(); |
| 2172 | } |
| 2173 | |
| 2174 | #define MIN_C320C_LEN 13 |
| 2175 | |
| 2176 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2177 | { |
| 2178 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2179 | int slotrank; |
| 2180 | int c320c; |
| 2181 | int stat[NUM_SLOTRANKS][256]; |
| 2182 | int delta = 0; |
| 2183 | |
| 2184 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2185 | |
| 2186 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2187 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2188 | } |
| 2189 | |
| 2190 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2191 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2192 | MCHBAR32(TC_RAP_ch(channel)) = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2193 | (ctrl->tRRD << 0) |
| 2194 | | (ctrl->tRTP << 4) |
| 2195 | | (ctrl->tCKE << 8) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2196 | | (ctrl->tWTR << 12) |
| 2197 | | (ctrl->tFAW << 16) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2198 | | (ctrl->tWR << 24) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2199 | | (ctrl->cmd_stretch[channel] << 30); |
| 2200 | |
| 2201 | if (ctrl->cmd_stretch[channel] == 2) |
| 2202 | delta = 2; |
| 2203 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2204 | delta = 4; |
| 2205 | |
| 2206 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2207 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2208 | } |
| 2209 | |
| 2210 | for (c320c = -127; c320c <= 127; c320c++) { |
| 2211 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2212 | ctrl->timings[channel][slotrank].pi_coding = c320c; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2213 | } |
| 2214 | program_timings(ctrl, channel); |
| 2215 | reprogram_320c(ctrl); |
| 2216 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2217 | stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2218 | } |
| 2219 | } |
| 2220 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2221 | struct run rn = get_longest_zero_run(stat[slotrank], 255); |
| 2222 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2223 | ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2224 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2225 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2226 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2227 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2228 | FOR_ALL_POPULATED_RANKS { |
| 2229 | ctrl->timings[channel][slotrank] = |
| 2230 | saved_timings[channel][slotrank]; |
| 2231 | } |
| 2232 | return MAKE_ERR; |
| 2233 | } |
| 2234 | } |
| 2235 | |
| 2236 | return 0; |
| 2237 | } |
| 2238 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2239 | /* |
| 2240 | * Adjust CMD phase shift and try multiple command rates. |
| 2241 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2242 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2243 | int command_training(ramctr_timing *ctrl) |
| 2244 | { |
| 2245 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2246 | |
| 2247 | FOR_ALL_POPULATED_CHANNELS { |
| 2248 | fill_pattern5(ctrl, channel, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2249 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2250 | } |
| 2251 | |
| 2252 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2253 | int cmdrate, err; |
| 2254 | |
| 2255 | /* |
| 2256 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2257 | * Issue: |
| 2258 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 2259 | * |
| 2260 | * Workaround: |
| 2261 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2262 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2263 | * |
| 2264 | * Single DIMM per channel: |
| 2265 | * Try command rate 1T and 2T |
| 2266 | */ |
| 2267 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2268 | if (ctrl->tCMD) |
| 2269 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2270 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2271 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2272 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2273 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2274 | |
| 2275 | if (!err) |
| 2276 | break; |
| 2277 | } |
| 2278 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2279 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2280 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2281 | return err; |
| 2282 | } |
| 2283 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2284 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | } |
| 2286 | |
| 2287 | FOR_ALL_POPULATED_CHANNELS |
| 2288 | program_timings(ctrl, channel); |
| 2289 | |
| 2290 | reprogram_320c(ctrl); |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2294 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2295 | { |
| 2296 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2297 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2298 | int lane; |
| 2299 | |
| 2300 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2301 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2302 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2303 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2304 | } |
| 2305 | program_timings(ctrl, channel); |
| 2306 | |
| 2307 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2308 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2309 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2310 | } |
| 2311 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2312 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2313 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2314 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2315 | write MR3 MPR enable |
| 2316 | in this mode only RD and RDA are allowed |
| 2317 | all reads return a predefined pattern */ |
| 2318 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 2319 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2320 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2321 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2322 | |
| 2323 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2324 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 2325 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x40411f4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2326 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2327 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2328 | |
| 2329 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2330 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2331 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2332 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2333 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2334 | |
| 2335 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2336 | MR3 disable MPR */ |
| 2337 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 2338 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2339 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2340 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2341 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2342 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2343 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2344 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2345 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2346 | |
| 2347 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2348 | stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2349 | } |
| 2350 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2351 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2352 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2353 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2354 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2355 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2356 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2357 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 2358 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2359 | return MAKE_ERR; |
| 2360 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2361 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2362 | } |
| 2363 | return 0; |
| 2364 | } |
| 2365 | |
| 2366 | int discover_edges(ramctr_timing *ctrl) |
| 2367 | { |
| 2368 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2369 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2370 | int channel, slotrank, lane; |
| 2371 | int err; |
| 2372 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2373 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2374 | |
| 2375 | toggle_io_reset(); |
| 2376 | |
| 2377 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2378 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2379 | } |
| 2380 | |
| 2381 | FOR_ALL_POPULATED_CHANNELS { |
| 2382 | fill_pattern0(ctrl, channel, 0, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2383 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2384 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2385 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2386 | } |
| 2387 | |
| 2388 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2389 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2390 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2391 | } |
| 2392 | |
| 2393 | program_timings(ctrl, channel); |
| 2394 | |
| 2395 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2396 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2397 | |
| 2398 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2399 | MR3 enable MPR |
| 2400 | write MR3 MPR enable |
| 2401 | in this mode only RD and RDA are allowed |
| 2402 | all reads return a predefined pattern */ |
| 2403 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 2404 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2405 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2406 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2407 | (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2408 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2409 | |
| 2410 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2411 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 2412 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2413 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2414 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2415 | |
| 2416 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2417 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2418 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2419 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2420 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2421 | (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2422 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2423 | |
| 2424 | /* DRAM command MRS |
| 2425 | * MR3 disable MPR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2426 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 2427 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2428 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2429 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2430 | (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2431 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2432 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2433 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2434 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2435 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2436 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2437 | } |
| 2438 | |
| 2439 | /* XXX: check any measured value ? */ |
| 2440 | |
| 2441 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2442 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2443 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2444 | } |
| 2445 | |
| 2446 | program_timings(ctrl, channel); |
| 2447 | |
| 2448 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2449 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2450 | |
| 2451 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2452 | MR3 enable MPR |
| 2453 | write MR3 MPR enable |
| 2454 | in this mode only RD and RDA are allowed |
| 2455 | all reads return a predefined pattern */ |
| 2456 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f000; |
| 2457 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2458 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2459 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2460 | (slotrank << 24) | 0x360004; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2461 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2462 | |
| 2463 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2464 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f105; |
| 2465 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x4041003; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2466 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2467 | (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2468 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2469 | |
| 2470 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2471 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2472 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2473 | 0x1001 | ((ctrl->CAS + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2474 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2475 | (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2476 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2477 | |
| 2478 | /* DRAM command MRS |
| 2479 | * MR3 disable MPR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2480 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f000; |
| 2481 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2482 | 0xc01 | (ctrl->tMOD << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2483 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2484 | (slotrank << 24) | 0x360000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2485 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2486 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2487 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2488 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2489 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2490 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2491 | } |
| 2492 | |
| 2493 | /* XXX: check any measured value ? */ |
| 2494 | |
| 2495 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2496 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2497 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2501 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2502 | } |
| 2503 | |
| 2504 | /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2505 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2506 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2507 | |
| 2508 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2509 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2510 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2511 | if (err) |
| 2512 | return err; |
| 2513 | } |
| 2514 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2515 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2516 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2517 | |
| 2518 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2519 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2520 | rising_edges[channel][slotrank]); |
| 2521 | if (err) |
| 2522 | return err; |
| 2523 | } |
| 2524 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2525 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2526 | |
| 2527 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2528 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2529 | falling_edges[channel][slotrank][lane]; |
| 2530 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2531 | rising_edges[channel][slotrank][lane]; |
| 2532 | } |
| 2533 | |
| 2534 | FOR_ALL_POPULATED_CHANNELS { |
| 2535 | program_timings(ctrl, channel); |
| 2536 | } |
| 2537 | |
| 2538 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2539 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2540 | } |
| 2541 | return 0; |
| 2542 | } |
| 2543 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2544 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2545 | { |
| 2546 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2547 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 2548 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2549 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2550 | int lane, i; |
| 2551 | int lower[NUM_LANES]; |
| 2552 | int upper[NUM_LANES]; |
| 2553 | int pat; |
| 2554 | |
| 2555 | FOR_ALL_LANES { |
| 2556 | lower[lane] = 0; |
| 2557 | upper[lane] = MAX_EDGE_TIMING; |
| 2558 | } |
| 2559 | |
| 2560 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2561 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2562 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 2563 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2564 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2565 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2566 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2567 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2568 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2569 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2570 | FOR_ALL_LANES { |
| 2571 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2572 | rising = edge; |
| 2573 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2574 | falling = edge; |
| 2575 | } |
| 2576 | program_timings(ctrl, channel); |
| 2577 | |
| 2578 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2579 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2580 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2581 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2582 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2583 | |
| 2584 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2585 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x1f006; |
| 2586 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2587 | 0x4 | (ctrl->tRCD << 16) | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2588 | (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2589 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2590 | (slotrank << 24) | 0x60000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2591 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x240; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2592 | |
| 2593 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2594 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; |
| 2595 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x8005020 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2596 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2597 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2598 | slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2599 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2600 | |
| 2601 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2602 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2603 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2604 | 0x4005020 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2605 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2606 | slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2607 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2608 | |
| 2609 | /* DRAM command PRE */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2610 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; |
| 2611 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2612 | 0xc01 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2613 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2614 | (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2615 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2616 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2617 | /* Execute command queue */ |
| 2618 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2619 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2620 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2621 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2622 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2623 | } |
| 2624 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2625 | /* FIXME: This register only exists on Ivy Bridge */ |
| 2626 | raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2627 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2628 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2629 | FOR_ALL_LANES { |
| 2630 | struct run rn; |
| 2631 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2632 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 2633 | |
| 2634 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2635 | |
| 2636 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 2637 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 2638 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2639 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2640 | |
| 2641 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2642 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2643 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2644 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2645 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2646 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 2647 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2648 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2649 | return MAKE_ERR; |
| 2650 | } |
| 2651 | } |
| 2652 | } |
| 2653 | } |
| 2654 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2655 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2656 | printram("CPA\n"); |
| 2657 | return 0; |
| 2658 | } |
| 2659 | |
| 2660 | int discover_edges_write(ramctr_timing *ctrl) |
| 2661 | { |
| 2662 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2663 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2664 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2665 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2666 | /* |
| 2667 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2668 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2669 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2670 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2671 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2672 | |
| 2673 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2674 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2675 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2676 | if (err) |
| 2677 | return err; |
| 2678 | } |
| 2679 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2680 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2681 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2682 | |
| 2683 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2684 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2685 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2686 | if (err) |
| 2687 | return err; |
| 2688 | } |
| 2689 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2690 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2691 | |
| 2692 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2693 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2694 | falling_edges[channel][slotrank][lane]; |
| 2695 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2696 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2697 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2698 | } |
| 2699 | |
| 2700 | FOR_ALL_POPULATED_CHANNELS |
| 2701 | program_timings(ctrl, channel); |
| 2702 | |
| 2703 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2704 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2705 | } |
| 2706 | return 0; |
| 2707 | } |
| 2708 | |
| 2709 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2710 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2711 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2712 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2713 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2714 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; |
| 2715 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2716 | (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2717 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; |
| 2718 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x0244; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2719 | |
| 2720 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2721 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x1f201; |
| 2722 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2723 | 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2724 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2725 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2726 | |
| 2727 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2728 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x1f105; |
| 2729 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2730 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2731 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x242; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2732 | |
| 2733 | /* DRAM command PRE */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2734 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x1f002; |
| 2735 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x1001 | (ctrl->tRP << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2736 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x60400; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2737 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2738 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2739 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2740 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2741 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2742 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2743 | } |
| 2744 | |
| 2745 | int discover_timC_write(ramctr_timing *ctrl) |
| 2746 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2747 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2748 | int i, pat; |
| 2749 | |
| 2750 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2751 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2752 | int channel, slotrank, lane; |
| 2753 | |
| 2754 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2755 | lower[channel][slotrank][lane] = 0; |
| 2756 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2757 | } |
| 2758 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2759 | /* |
| 2760 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2761 | * FIXME: This must only be done on Ivy Bridge. |
| 2762 | */ |
| 2763 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2764 | printram("discover timC write:\n"); |
| 2765 | |
| 2766 | for (i = 0; i < 3; i++) |
| 2767 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2768 | |
| 2769 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 2770 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 2771 | ~0x3f000000, rege3c_b24[i] << 24); |
| 2772 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2773 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2774 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2775 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2776 | FOR_ALL_POPULATED_RANKS { |
| 2777 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2778 | u32 raw_stats[MAX_TIMC + 1]; |
| 2779 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2780 | |
| 2781 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2782 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2783 | |
| 2784 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2785 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
| 2786 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2787 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2788 | FOR_ALL_LANES { |
| 2789 | ctrl->timings[channel][slotrank] |
| 2790 | .lanes[lane].timC = timC; |
| 2791 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2792 | program_timings(ctrl, channel); |
| 2793 | |
| 2794 | test_timC_write (ctrl, channel, slotrank); |
| 2795 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2796 | /* FIXME: Another IVB-only register! */ |
| 2797 | raw_stats[timC] = |
Angel Pons | 1aba2a3 | 2020-01-05 22:31:41 +0100 | [diff] [blame] | 2798 | MCHBAR32(0x436c + channel * 0x400); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2799 | } |
| 2800 | FOR_ALL_LANES { |
| 2801 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2802 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2803 | stats[timC] = !!(raw_stats[timC] |
| 2804 | & (1 << lane)); |
| 2805 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2806 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2807 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2808 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2809 | printk(BIOS_EMERG, |
| 2810 | "timC write discovery failed: " |
| 2811 | "%d, %d, %d\n", channel, |
| 2812 | slotrank, lane); |
| 2813 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2814 | return MAKE_ERR; |
| 2815 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2816 | printram("timC: %d, %d, %d: " |
| 2817 | "0x%02x-0x%02x-0x%02x, " |
| 2818 | "0x%02x-0x%02x\n", channel, slotrank, |
| 2819 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2820 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2821 | rn.end - ctrl->timC_offset[i]); |
| 2822 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2823 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2824 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2825 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2826 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2827 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2828 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2829 | upper[channel][slotrank][lane]); |
| 2830 | |
| 2831 | } |
| 2832 | } |
| 2833 | } |
| 2834 | } |
| 2835 | |
| 2836 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2837 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2838 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2839 | udelay(2); |
| 2840 | } |
| 2841 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2842 | /* |
| 2843 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2844 | * FIXME: This must only be done on Ivy Bridge. |
| 2845 | */ |
| 2846 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2847 | |
| 2848 | printram("CPB\n"); |
| 2849 | |
| 2850 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2851 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2852 | (lower[channel][slotrank][lane] + |
| 2853 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2854 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2855 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2856 | (lower[channel][slotrank][lane] + |
| 2857 | upper[channel][slotrank][lane]) / 2; |
| 2858 | } |
| 2859 | FOR_ALL_POPULATED_CHANNELS { |
| 2860 | program_timings(ctrl, channel); |
| 2861 | } |
| 2862 | return 0; |
| 2863 | } |
| 2864 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2865 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2866 | { |
| 2867 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2868 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2869 | |
| 2870 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2871 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2872 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2873 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2874 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2875 | printram("normalize %d, %d, %d: mat %d\n", |
| 2876 | channel, slotrank, lane, mat); |
| 2877 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2878 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2879 | printram("normalize %d, %d, %d: delta %d\n", |
| 2880 | channel, slotrank, lane, delta); |
| 2881 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2882 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2883 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2884 | } |
| 2885 | |
| 2886 | FOR_ALL_POPULATED_CHANNELS { |
| 2887 | program_timings(ctrl, channel); |
| 2888 | } |
| 2889 | } |
| 2890 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2891 | void write_controller_mr(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2892 | { |
| 2893 | int channel, slotrank; |
| 2894 | |
| 2895 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2896 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2897 | make_mr0(ctrl, slotrank); |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2898 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2899 | make_mr1(ctrl, slotrank, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2900 | } |
| 2901 | } |
| 2902 | |
| 2903 | int channel_test(ramctr_timing *ctrl) |
| 2904 | { |
| 2905 | int channel, slotrank, lane; |
| 2906 | |
| 2907 | slotrank = 0; |
| 2908 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2909 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2910 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2911 | return MAKE_ERR; |
| 2912 | } |
| 2913 | FOR_ALL_POPULATED_CHANNELS { |
| 2914 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 2915 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2916 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2917 | } |
| 2918 | |
| 2919 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2920 | FOR_ALL_CHANNELS |
| 2921 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2922 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2923 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2924 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2925 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2926 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2927 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2928 | /* DRAM command ACT */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2929 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = 0x0001f006; |
| 2930 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x0028a004; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2931 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2932 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000244; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2933 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2934 | /* DRAM command WR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2935 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = 0x0001f201; |
| 2936 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281064; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2937 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2938 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2939 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2940 | /* DRAM command RD */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2941 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = 0x0001f105; |
| 2942 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x04281064; |
Angel Pons | 63ae8de | 2020-01-10 02:03:47 +0100 | [diff] [blame] | 2943 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2944 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000242; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2945 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2946 | /* DRAM command PRE */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2947 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 3)) = 0x0001f002; |
| 2948 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 3)) = 0x00280c01; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2949 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2950 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 3)) = 0x00000240; |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2951 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2952 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2953 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2954 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2955 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2956 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2957 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2958 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2959 | channel, slotrank, lane); |
| 2960 | return MAKE_ERR; |
| 2961 | } |
| 2962 | } |
| 2963 | return 0; |
| 2964 | } |
| 2965 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2966 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2967 | { |
| 2968 | int channel; |
| 2969 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2970 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2971 | static u32 seeds[NUM_CHANNELS][3] = { |
| 2972 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 2973 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 2974 | }; |
| 2975 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2976 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2977 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 2978 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 2979 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2980 | } |
| 2981 | } |
| 2982 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 2983 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2984 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2985 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2986 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2987 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2988 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2989 | } |
| 2990 | } |
| 2991 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2992 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2993 | { |
| 2994 | int channel; |
| 2995 | |
| 2996 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2997 | /* Always drive command bus */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2998 | MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2999 | } |
| 3000 | |
| 3001 | udelay(1); |
| 3002 | |
| 3003 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3004 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3005 | } |
| 3006 | } |
| 3007 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3008 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3009 | { |
| 3010 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3011 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3012 | FOR_ALL_POPULATED_CHANNELS { |
| 3013 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3014 | int min_pi = 10000; |
| 3015 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3016 | |
| 3017 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3018 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 3019 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3020 | } |
| 3021 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3022 | b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3023 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3024 | b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3025 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3026 | dram_odt_stretch(ctrl, channel); |
| 3027 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3028 | MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 3029 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3030 | } |
| 3031 | } |
| 3032 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3033 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3034 | { |
| 3035 | int channel; |
| 3036 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3037 | MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; |
| 3038 | MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3039 | } |
| 3040 | } |
| 3041 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3042 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 3043 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3044 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3045 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3046 | } |
| 3047 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3048 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3049 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3050 | { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3051 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 3052 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3053 | int channel; |
| 3054 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3055 | int t3_ns; |
| 3056 | u32 r32; |
| 3057 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3058 | /* FIXME: This register only exists on Ivy Bridge */ |
| 3059 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3060 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3061 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3062 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3063 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3064 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3065 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3066 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3067 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3068 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3069 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3070 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3071 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3072 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3073 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3074 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3075 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3076 | |
| 3077 | FOR_ALL_CHANNELS { |
| 3078 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3079 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3080 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3081 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3082 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3083 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3084 | case 1: |
| 3085 | case 4: |
| 3086 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3087 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3088 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3089 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3090 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3091 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3092 | break; |
| 3093 | } |
| 3094 | } |
| 3095 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3096 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3097 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3098 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3099 | |
| 3100 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3101 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3102 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3103 | MCHBAR32_OR(MC_INIT_STATE_G, 1); |
| 3104 | MCHBAR32_OR(MC_INIT_STATE_G, 0x80); |
| 3105 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3106 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3107 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3108 | FOR_ALL_POPULATED_CHANNELS |
| 3109 | break; |
| 3110 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3111 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3112 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3113 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3114 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3115 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3116 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3117 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3118 | t1_ns += 500; |
| 3119 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3120 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3121 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3122 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3123 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3124 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3125 | t3_ns = 500; |
| 3126 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3127 | |
| 3128 | /* The graphics driver will use these watermark values */ |
| 3129 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
| 3130 | MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, |
| 3131 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 3132 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3133 | } |
| 3134 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3135 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3136 | { |
| 3137 | int channel, slotrank, lane; |
| 3138 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3139 | FOR_ALL_POPULATED_CHANNELS { |
| 3140 | MCHBAR32(TC_RAP_ch(channel)) = |
| 3141 | (ctrl->tRRD << 0) |
| 3142 | | (ctrl->tRTP << 4) |
| 3143 | | (ctrl->tCKE << 8) |
| 3144 | | (ctrl->tWTR << 12) |
| 3145 | | (ctrl->tFAW << 16) |
| 3146 | | (ctrl->tWR << 24) |
| 3147 | | (ctrl->cmd_stretch[channel] << 30); |
| 3148 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3149 | |
| 3150 | udelay(1); |
| 3151 | |
| 3152 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3153 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3154 | } |
| 3155 | |
| 3156 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3157 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3158 | } |
| 3159 | |
| 3160 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3161 | MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3162 | |
| 3163 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3164 | udelay(1); |
| 3165 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3166 | } |
| 3167 | |
| 3168 | printram("CPE\n"); |
| 3169 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3170 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3171 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3172 | |
| 3173 | printram("CP5b\n"); |
| 3174 | |
| 3175 | FOR_ALL_POPULATED_CHANNELS { |
| 3176 | program_timings(ctrl, channel); |
| 3177 | } |
| 3178 | |
| 3179 | u32 reg, addr; |
| 3180 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3181 | /* Poll for RCOMP */ |
| 3182 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 3183 | ; |
| 3184 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3185 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3186 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3187 | } while ((reg & 0x14) == 0); |
| 3188 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3189 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3190 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3191 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3192 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3193 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3194 | udelay(500); |
| 3195 | |
| 3196 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3197 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3198 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3199 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3200 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3201 | MCHBAR32(addr) = reg; |
| 3202 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3203 | /* Wait 10ns for ranks to settle */ |
| 3204 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3205 | |
| 3206 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3207 | MCHBAR32(addr) = reg; |
| 3208 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3209 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3210 | write_reset(ctrl); |
| 3211 | } |
| 3212 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3213 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3214 | dram_mrscommands(ctrl); |
| 3215 | |
| 3216 | printram("CP5c\n"); |
| 3217 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3218 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3219 | |
| 3220 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3221 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3222 | udelay(2); |
| 3223 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3224 | } |