Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 4 | #include <symbols.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 5 | #include <amdblocks/reset.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 6 | #include <bootblock_common.h> |
| 7 | #include <console/console.h> |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 8 | #include <cpu/x86/cache.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/amd/msr.h> |
| 11 | #include <cpu/x86/mtrr.h> |
| 12 | #include <cpu/amd/mtrr.h> |
Kangheui Won | 1464b0e | 2020-09-17 17:04:12 +1000 | [diff] [blame] | 13 | #include <cpu/x86/tsc.h> |
Martin Roth | 50cca76 | 2020-08-13 11:06:18 -0600 | [diff] [blame] | 14 | #include <pc80/mc146818rtc.h> |
| 15 | #include <soc/psp_transfer.h> |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 16 | #include <soc/southbridge.h> |
| 17 | #include <soc/i2c.h> |
| 18 | #include <amdblocks/amd_pci_mmconf.h> |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 19 | #include <acpi/acpi.h> |
Martin Roth | 95d05e4 | 2020-06-24 19:42:44 -0600 | [diff] [blame] | 20 | |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 21 | asmlinkage void bootblock_resume_entry(void); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 22 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 23 | /* PSP performs the memory training and setting up DRAM map prior to x86 cores |
| 24 | being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, |
| 25 | route lower memory addresses covered by fixed MTRRs to DRAM except for |
| 26 | 0xa0000-0xc0000 . */ |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 27 | static void set_caching(void) |
| 28 | { |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 29 | msr_t top_mem; |
| 30 | msr_t sys_cfg; |
| 31 | msr_t mtrr_def_type; |
| 32 | msr_t fixed_mtrr_ram; |
| 33 | msr_t fixed_mtrr_mmio; |
| 34 | struct var_mtrr_context mtrr_ctx; |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 35 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 36 | var_mtrr_context_init(&mtrr_ctx, NULL); |
| 37 | top_mem = rdmsr(TOP_MEM); |
| 38 | /* Enable RdDram and WrDram attributes in fixed MTRRs. */ |
| 39 | sys_cfg = rdmsr(SYSCFG_MSR); |
| 40 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 41 | |
| 42 | /* Fixed MTRR constants. */ |
| 43 | fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = |
| 44 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | |
| 45 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | |
| 46 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | |
| 47 | ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); |
| 48 | fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = |
| 49 | ((MTRR_TYPE_UNCACHEABLE) << 0) | |
| 50 | ((MTRR_TYPE_UNCACHEABLE) << 8) | |
| 51 | ((MTRR_TYPE_UNCACHEABLE) << 16) | |
| 52 | ((MTRR_TYPE_UNCACHEABLE) << 24); |
| 53 | |
| 54 | /* Prep default MTRR type. */ |
| 55 | mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); |
| 56 | mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; |
| 57 | mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; |
| 58 | mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; |
| 59 | |
| 60 | disable_cache(); |
| 61 | |
| 62 | wrmsr(SYSCFG_MSR, sys_cfg); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 63 | |
| 64 | clear_all_var_mtrr(); |
| 65 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 66 | var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); |
| 67 | var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 68 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 69 | /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ |
| 70 | wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); |
| 71 | wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); |
| 72 | wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); |
| 73 | wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); |
| 74 | wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); |
| 75 | wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); |
| 76 | wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); |
| 77 | wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); |
| 78 | wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); |
| 79 | wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); |
| 80 | wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 81 | |
Aaron Durbin | d6161d4 | 2020-06-04 19:57:54 -0600 | [diff] [blame] | 82 | wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); |
| 83 | |
| 84 | /* Enable Fixed and Variable MTRRs. */ |
| 85 | sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; |
| 86 | sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; |
| 87 | /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once |
| 88 | MP init happens in coreboot proper it can be knocked down. */ |
| 89 | wrmsr(SYSCFG_MSR, sys_cfg); |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 90 | |
| 91 | enable_cache(); |
| 92 | } |
| 93 | |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 94 | static void write_resume_eip(void) |
| 95 | { |
| 96 | msr_t s3_resume_entry = { |
| 97 | .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, |
| 98 | .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, |
| 99 | }; |
| 100 | |
| 101 | /* |
| 102 | * Writing to the EIP register can only be done once, otherwise a fault is triggered. |
| 103 | * When this register is written, it will trigger the microcode to stash the CPU state |
| 104 | * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be |
| 105 | * restored and execution will continue at the EIP. |
| 106 | */ |
| 107 | if (!acpi_is_wakeup_s3()) |
| 108 | wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); |
| 109 | } |
| 110 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 111 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 112 | { |
Felix Held | d149f1d | 2020-04-04 02:48:03 +0200 | [diff] [blame] | 113 | set_caching(); |
Raul E Rangel | ec26428 | 2020-06-04 16:42:50 -0600 | [diff] [blame] | 114 | write_resume_eip(); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 115 | enable_pci_mmconf(); |
| 116 | |
Kangheui Won | 1464b0e | 2020-09-17 17:04:12 +1000 | [diff] [blame] | 117 | /* |
| 118 | * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz |
| 119 | * when we use micro-seconds granularity for Zork |
| 120 | */ |
| 121 | base_timestamp /= tsc_freq_mhz(); |
| 122 | |
| 123 | if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) |
| 124 | boot_with_psp_timestamp(base_timestamp); |
| 125 | |
| 126 | /* |
| 127 | * if VBOOT_STARTS_BEFORE_BOOTBLOCK is not selected or |
| 128 | * previous step did nothing, proceed with normal bootblock main. |
| 129 | */ |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 130 | bootblock_main_with_basetime(base_timestamp); |
| 131 | } |
| 132 | |
| 133 | void bootblock_soc_early_init(void) |
| 134 | { |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 135 | fch_pre_init(); |
| 136 | } |
| 137 | |
| 138 | void bootblock_soc_init(void) |
| 139 | { |
| 140 | u32 val = cpuid_eax(1); |
| 141 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 142 | |
Martin Roth | 4b34193 | 2020-10-06 15:29:28 -0600 | [diff] [blame] | 143 | if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { |
| 144 | verify_psp_transfer_buf(); |
Martin Roth | 0f3ef70 | 2020-10-06 18:11:12 -0600 | [diff] [blame] | 145 | show_psp_transfer_info(); |
Martin Roth | 95d05e4 | 2020-06-24 19:42:44 -0600 | [diff] [blame] | 146 | } |
Martin Roth | 95d05e4 | 2020-06-24 19:42:44 -0600 | [diff] [blame] | 147 | |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 148 | fch_early_init(); |
Felix Held | 4667322 | 2020-04-04 02:37:04 +0200 | [diff] [blame] | 149 | } |